Time-to-market and the ability to “tweak” an existing design to achieve that next level of performance are paramount for system architects, board designers, layout engineers, and others responsible for developing high-performance, cost-sensitive, dependable systems. But if you’re reading this, you understand the frustrations and challenges in trying to meet those goals with traditional memory options.
The design-to-market time requirements vary greatly by industry but are all directly related to the complexity of a design. I work with memory every day, and to me, the interface seems straightforward and simple. But over the years, systems designers continue to ask, “Why is the memory interface so complex, and why does it keep changing every three to four years?” They have a point. Nearly 15 years ago, DDR was introduced, and the typical memory data sheet went from about 20 pages for SDR to about 60 pages for DDR. Now, the leading-edge DDR4 data sheet is over 200 pages with countless timing parameters supporting different speed grades.
With the first 2GB Hybrid Memory Cube (HMC) samples now shipping, it’s a good time to highlight the standout features of HMC—including HMC’s ability to reduce complexity with its abstracted interface.
In my next post, I’ll highlight why many companies have already selected HMC as the backbone of their designs. When you see the difference between HMC and traditional memory in terms of board footprint, channel complexity, power consumption, and energy per bit, I’m willing to bet you’ll be a believer too. So stay tuned! And in the meantime, if you have any questions about HMC or have issues you’d like us to talk about in future posts, please leave a comment below.