Buzz from the Linley Tech Processor Conference – HMC and More

By Jay Walstrum - 2013-10-31

The week before last, I traveled 20 minutes down Highway 101 from Micron’s San Jose offices to Santa Clara to attend the 7th Annual Linley Tech Processor Conference. The small (just over 400 participants), two-day event was like a breath of fresh air compared to some of the more massive conferences that I’ve attended. There were some targeted OEMs and a smattering of industry media, but most of the attendees were real engineers trying to solve real problems.

The keynote session covered trends affecting processors in communications systems. Experts from industry-leading companies shared over 20 technical presentations. I took a turn during the High-Performance Memories for Networking session to give an overview of Hybrid Memory Cube (HMC) and its benefits for networking applications. I fielded several great questions after my presentation, but it was a conversation during lunch that made my day. One conference attendee said that when tasked with running a particular application scheme, he was able to recognize a 15X improvement in bandwidth with Micron’s HMC compared to an existing technology. ”And that was our direct analysis—not marketing jargon from a web site,” he said earnestly.

When I wasn’t evangelizing the merits of HMC, I attended some excellent sessions. ARM was a popular platform, and software-defined networks (SDNs) generated significant buzz (as reported by Charlie Ashton on, along with FPGAs, which give companies more flexibility to create differentiated products and speed time to market. Discussions also surfaced around these questions:

  • What is the next optimized solution or integration that will bring higher value to memory?  
  • Will memory subsystems look like SND projects, separating control plane and data path? And will the value of integrated memory subsystems diminish, or can abstracted interfaces provide optimized memory solutions for both control and data?

It was gratifying to see members of this segment embracing new architectures and new ways of looking at age-old issues like processors in the data center and complex networking applications.

It was also exciting to see the interest in HMC taking hold now that it’s really tangible. It’s hard to believe that only two years ago, the HMC Consortium (HMCC) was just getting off the ground. Today, the HMCC has more than 100 adopters and a specification that’s available to the public. And of course, I would be remiss if I didn’t mention that Micron is now shipping the world’s first 2GB HMC engineering samples! When someone asked if Micron is ready to support a product of this magnitude, my answer was: “We’re absolutely ready!” 

Visit us next month in Denver at Supercomputing 2013 for more exciting developments around HMC and other emerging Micron technologies.

Jay Walstrum, Senior System Architect at Micron

Jay Walstrum

Jay Walstrum

Jay Walstrum is a Senior System Architect for Micron’s Compute and Networking Business Unit, where he is focusing on new opportunities in the three to five-plus year timeframe. In his role, he also applies innovative technologies and memory architectures to solve customer system-level challenges.

Jay’s responsibilities include working closely with a market-strategy team to identify new technology, applications, product/architecture specifications, customers, and markets for new product concepts. He also actively works with customer system architects, technologists, third-party developers, and Micron’s Research and Development team to identify, define, and architect innovative memory solutions.

Before beginning with Micron in January 2013, Jay spent 22 years at Xilinx Corp, where he held various positions ranging from the Director of Quality, to the Senior Product Planning Manager, to the Strategic and Technical Marketing Leader.

Jay holds a BSEE from University of Southern California. He holds 11 patents in the areas of FPGA system Solutions and memory interface architecture.