HMC Arrives Just in Time to Be Your New Standard for Memory Performance: Part 3

By Tom Kinsley - 2013-11-20

Back again with part 3 of my blog series outlining the features and benefits of Micron’s HMC.  My last post covered HMC’s abstracted memory management, simplified and scalable interface, and superior performance.  Let’s finish up by discussing these additional key features:

Uncomplicated Board Layout and Dense Package

Our short-reach (SR) HMC device comes in two packages: the four-link, 31mm x 31mm package and the smaller two-link, 16mm x 19.5mm package, which are each available in 2GB and 4GB densities. Depending on the number of links routed and the configuration of each link (each link can be configured for different widths), the HMC can have as few as 34 and up to 66 active signals per channel and four additional active signals per cube. As such, fewer signals need to be routed, and it’s easy to route them on standard FR4 material with the good return/insertion loss of the PHY, full-lane reversal, and lane polarity options. HMC’s routing is not only simple and scalable to exact density or bandwidth requirements, its small packages also take up very little real estate on the PCB.

Exceptional RAS Features

Some of the more well-known reliability, availability, and serviceability (RAS) features of the cube are the robust 32-bit cyclic redundancy check (CRC) protection and packet retry mechanisms over the external channels.  But several other significant features set HMC apart, including: built-in self-tests (BISTs) and memory scrubbing that detect and repair soft and hard memory or potential through-silicon via (TSV) failures; internal thermal sensing that optimizes refresh control; error status registers with status flags; and reporting options through either in-band or two-sided band channels.  Basically, we’ve built all of the default functions (and more) of a mission-critical CPU into the HMC device, which helps reduce the overall cost of silicon for the system.


While HMC may cost more than an equivalent-density DDRx module, let’s look at the upside. In addition to all of the benefits already discussed, at like-bandwidth, HMC requires less ASIC or CPU silicon, enables the overall system to consume less power—which also equates to lower cooling costs—and, thanks to HMC’s on-device RAS features, experiences a higher percentage of uptime without high service or replacement costs for defective memory.

Stable Technology and Long-Term Support   

With traditional memory, system designers often ask, “Why does the memory interface keep changing every three to four years?” With HMC, it’s different! Micron and the HMCC are working on next-generation HMC product lines with the goal of keeping future devices as compatible as possible with older devices. Next-generation HMC products will support higher-density and faster PHYs while using the same protocol, side-band channels, internal register, and addressing—and still be totally independent to the memory technology within. And because many of our customers need long-term memory support, and just like SDR, our HMC will be supported in the long term.

The Time is Now

If you need real memory bandwidth, mission-critical reliability, reusable IP, and year-over-year savings—and need it all now—contact us today to see how HMC can help take your design to the next level. 

And come talk to us at SC13—and see our HMC live demos—on November 18-21, in Denver, CO, at booth 1322.

Tom Kinsley

Tom Kinsley

Tom Kinsley is a memory development engineer at Micron Technology. He is currently engaged in the development and enablement of the next-generation memory including Micron’s hybrid memory cube.

Mr. Kinsley joined Micron in 1988 and has held a variety of product design engineering roles. Some of his accomplishments in these roles include working on the development of IBM PC/AT and XT memory expansion cards, Apple Macintosh video cards and early memory modules SIMM (single in-line memory module).

Additionally, Mr. Kinsley holds more than 10 patents in the area of electronics engineering.