Memory

Improving Ultrathin Boot Performance with Quad I/O

By Redge Villanueva - 2013-01-02

In today’s fast-paced world, consumers need faster system boot times in their ultrathin devices. But other advanced system features, like security, can interfere with boot-time performance targets, posing a challenge to ultrathin designers. The new quad I/O feature in Micron’s N25Q SPI NOR Flash memory can help. N25Q SPI NOR is the first in the market to support quad I/O mode at a 108 MHz clock rate, reaching read transfer rates up to 54 MB/s and improving read bandwidth up to 85% compared to single I/O reads at 50 MHz.

Implementing the N25Q quad I/O feature of x1 instruction/ x4 address/x4 data is easy—designers simply issue the quad I/O commands (such as EBh opcode)—you don’t even need to configure the device. Our advanced N25Q device also supports basic functionality such as single or dual I/O reads, allowing systems to do slower read operations according the needs of the ultrathin application.

Available in 32Mb, 64Mb, 128Mb, and up to 1Gb densities, quad I/O-equipped N25Q SPI NOR is quickly becoming the technology of choice for the ultrathin market, including Intel Ultrabooks™ and AMD ultrathin laptops.

 

Redge Villanueva

Redge Villanueva

Redge Villanueva is a Senior Ecosystem Enabling Manager at Micron enabling Micron memories on chipset platforms for embedded applications. She has worked in various engineering and marketing roles within the memory industry for over 23 years.
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