Innovations // Memory

ISC12: Clocking Sequoia, the World's #1 Supercomputer

By Dean Klein - 2012-06-22

In yesterday’s post, I promised to dish on what I learned about the new #1 Top500 supercomputer, Sequoia, from the IBM and Lawrence Livermore National Labs folks who built it. Sequoia is built around IBM’s Power6 CPU and BlueGene-Q architecture. This CPU has 18 cores on a chip, with one core dedicated to running Linux, one core for a spare, and 16 cores dedicated for computation. The CPUs are clocked at a conservative 1.6 GHz and are water-cooled. The CPUs are assembled onto a module that contains one other significant feature—72 DDR3 memory devices. Most notable for me was that these were Micron memory devices. According to IBM, the aggregate bandwidth of the CPU chip clocks in at just over 42 GB/s. The CPU heat sink extends over the memory on one side of the module, providing water cooling for the memory, too. IBM says the machine is 90% water-cooled and 10% air-cooled, which makes the machine pretty quiet, unlike most servers. Nice! (Or cool!) Besides taking the performance crown, IBM is also claiming the energy-efficiency lead with the BlueGene-Q architecture. My calculations show Sequoia to be a “modest” 0.483 watts per floating point operation (FLOP), which is less than half that of the Japanese K Computer that held the top ranking in 2011. Sequoia’s combined 1.5+ million cores(!) and 1.6  million gigabytes (1.6 petabytes) churn out a peak performance of over 20 petaflops (20x10^15 PFLOPS) and a Linpack benchmark score of over 16 petaflops. That nets out to a computational efficiency of about 80%, a good score. IBM claims this architecture can scale to 100 PFLOPS (peak), but could anyone afford the 40MW power bill? It is worthwhile to note that there are now four IBM BlueGene-Q supercomputers in the top 10 of the Top500 list (#1, #3, #7, and #8). A very impressive showing for IBM! Stay tuned for the next blog post to find out about Fujitsu’s supercomputing efforts, plus the latest on future supercomputing technologies.

Dean Klein

Dean Klein

Dean Klein is Vice President of Memory System Development at Micron Technology. Mr. Klein joined Micron in January 1999, after having held several leadership positions at Micron Electronics, Inc., including Executive Vice President of Product Development and Chief Technical Officer. He also co-founded and served as President of PC Tech, Inc., previously a wholly-owned subsidiary of Micron Electronics, Inc., from its inception in 1984. Mr. Klein’s current responsibilities as Vice President of Memory System Development focus on developing memory technologies and capabilities.

Mr. Klein earned a Bachelor of Science degree in electrical engineering and a Master of Electrical Engineering from the University of Minnesota, and he holds over 220 patents in the areas of computer architecture and electrical engineering. He has a passion for math and science education and is a mentor to the FIRST Robotics team ( in the Meridian, Idaho school district.