20nm NAND—Smaller and Better

By Kevin Kilbuck - 2011-04-14

Today, Intel and Micron announced our latest advancement of NAND process technology—20nm NAND. Our new device crams 8GB into about 40% less die area than our already-tiny 25nm NAND. That’s small enough to make it the first 8GB MLC die that can fit into a microSD® card. You can see the difference in the photo below. This shrink is well ahead of our competitors (some have just announced production on a process equivalent to our 25nm) and keeps us solidly in the leadership position for NAND development. But the really remarkable thing is what we’ve been able do for quality and endurance. To understand why this is significant, you need to know a little about NAND scaling.

Process shrinks require tinier, more-complex cells, which translates to lower performance and endurance. This has been true for generations of NAND process shrinks and is more or less a byproduct of the laws of physics. We’re approaching atomic dimensions (a single copper atom is .25nm), and it takes some extraordinary science to design circuits that can hold electrical charges at this scale. With this new design however, we included some innovative new technology that will allow our 20nm NAND to eventually hit the same endurance and performance specifications as our current-generation NAND (25nm). We're also continuing our pattern of keeping ECC (error correction code) requirements a generation lower than the competition. Our 20nm NAND will have similar ECC requirements to some competitors’ current NAND products, meaning they won't require more ECC from the controller. These are significant advancements that helps provide a viable path for NAND scaling and development. The end result is a great new product that’s going to enable even more innovation in mobile storage applications.

Kevin Kilbuck

Kevin Kilbuck

Kevin is Micron Technology's Director of NAND Marketing.