| File |
Title and Description  |
ID Number |
Last Update |
Software Downloads |
 |
TN-49-03: RLDRAM II Clocking Strategies TN-49-03: RLDRAM II Clocking Strategies
- Addresses the operation of the RLDRAM II device outside the specified range of clock periods and the timing changes that occur in this mode of operation. |
TN4903 |
2007-05-01T00:00:00-06:00May 2007 |
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TN-49-04: Calculating Memory System Power for RLDRAM IITN-49-04: Calculating Memory System Power for RLDRAM II
- Details how RLDRAM II devices consume power and provides tools to estimate power consumption. |
TN-49-04 |
2007-11-01T00:00:00-06:00Nov 2007 |
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TN-49-02: Exploring the RLDRAM II Feature SetTN-49-02: Exploring the RLDRAM II Feature Set
- Outlines the performance-enhancing features offered by RLDRAM II architecture |
TN-49-02 |
2006-01-01T00:00:00-07:00Jan 2006 |
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TN-49-01: RLDRAM II Design GuideTN-49-01: RLDRAM II Design Guide
- Describes the general features of circuit implementations using RLDRAM memory architecture |
TN-49-01 |
2006-01-01T00:00:00-07:00Jan 2006 |
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TN-48-16: Product Replacement for x32 EOL SDRAMsTN-48-16: Product Replacement for x32 EOL SDRAMs
- Outlines recommendations for replacing or transitioning away from high density, x32 components that are nearing end of production. |
TN-48-16 |
2006-07-01T00:00:00-06:00Jul 2006 |
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TN-48-15: Backward Compatibility for Faster SDRAMTN-48-15: Backward Compatibility for Faster SDRAM
- Reviews the timing differences between SDRAM generations and shows how the faster Micron parts are compatible with the slower parts |
TN-48-15 |
2005-10-01T00:00:00-06:00Oct 2005 |
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TN-48-12: Interfacing SDRAM Devices with Motorola's MPC8xxTN-48-12: Interfacing SDRAM Devices with Motorola's MPC8xx |
TN-48-12 |
2002-02-01T00:00:00-07:00Feb 2002 |
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TN-48-10: Mobile SDRAM's Power-Saving FeaturesTN-48-10: Mobile SDRAM's Power-Saving Features |
TN-48-10 |
2002-06-01T00:00:00-06:00Jun 2002 |
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TN-48-09: LVTTL Derating for SDRAM Slew Rate ViolationsTN-48-09: LVTTL Derating for SDRAM Slew Rate Violations |
TN-48-09 |
2000-10-01T00:00:00-06:00Oct 2000 |
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TN-48-08: Designing in SDRAM for Future UpgradesTN-48-08: Designing in SDRAM for Future Upgrades |
TN-48-08 |
2004-03-01T00:00:00-07:00Mar 2004 |
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TN-48-06: Increasing Battery Life in LaptopsTN-48-06: Increasing Battery Life in Laptops |
TN-48-06 |
2000-02-01T00:00:00-07:00Feb 2000 |
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TN-48-05: SDRAM WRITE to ACTIVE Command Timing TN-48-05: SDRAM WRITE to ACTIVE Command Timing |
TN-48-05 |
2000-11-01T00:00:00-06:00Nov 2000 |
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TN-48-04: Is Your Module PC100?TN-48-04: Is Your Module PC100?
- Explains how to determine if a module using Micron SDRAMs is PC100-compliant. The speed designator on the SDRAM component does not necessarily reflect the system application speed of the module. |
TN-48-04 |
1999-02-01T00:00:00-07:00Feb 1999 |
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TN-48-03: Designing for High Performance With Synchronous DRAM ModulesTN-48-03: Designing for High Performance With Synchronous DRAM Modules |
TN-48-03 |
1999-02-01T00:00:00-07:00Feb 1999 |
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TN-48-01: Examples of READ-MODIFY-WRITE Cycles With Synchronous DRAMsTN-48-01: Examples of READ-MODIFY-WRITE Cycles With Synchronous DRAMs |
TN-48-01 |
1999-02-01T00:00:00-07:00Feb 1999 |
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TN-47-23: Advantages of DDR2 Differential DQS SignalingTN-47-23: Advantages of DDR2 Differential DQS Signaling
- Focuses on the benefits the differential DQS signaling feature provides and explains how to design with it |
TN-47-23 |
2008-03-01T00:00:00-07:00Mar 2008 |
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TN-47-22: Designing for 1.5V, Low-Power FBDIMMsTN-47-22: Designing for 1.5V, Low-Power FBDIMMs
- Discusses memory power trends and identifies new low-voltage solutions for high-density DDR2 memory designs |
TN-47-22 |
2008-02-01T00:00:00-07:00Feb 2008 |
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TN-47-21: FBDIMM – Channel Utilization (Bandwidth and Power)TN-47-21: FBDIMM – Channel Utilization (Bandwidth and Power)
- Newly introduced FBDIMMs offer virtually unlimited scalability of density, a significantly reduced number of routed motherboard signals, and high bandwidth solutions, all with an extremely reliable channel protocol. |
TN-47-21 |
2006-10-01T00:00:00-06:00Oct 2006 |
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TN-47-20: DDR2 (Point-to-Point) Package Sizes and Layout BasicsTN-47-20: DDR2 (Point-to-Point) Package Sizes and Layout Basics
- General guidelines for developing the PCB floor plan. |
TN-47-20 |
2006-05-01T00:00:00-06:00May 2006 |
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TN-47-19: DDR2 (Point-to-Point) Features and Functionality TN-47-19: DDR2 (Point-to-Point) Features and Functionality
- Focuses on the unique memory requirements of point-to-point design layouts and describes DDR2 features and functionality. |
TN-47-19 |
2006-04-01T00:00:00-06:00Apr 2006 |
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TN-47-17: DDR2 SODIMM Optimized Address/Command NetsTN-47-17: DDR2 SODIMM Optimized Address/Command Nets
- Provides the system-level designer with an overview of the DDR2 SODIMM family and offers insight into termination techniques utilized on the commands and addresses for these modules |
TN-47-17 |
2005-05-01T00:00:00-06:00May 2005 |
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TN-47-16: Designing for High-Density DDR2 Memory TN-47-16: Designing for High-Density DDR2 Memory
- Focuses on designing for high-density memory—addressing schemes of each density, configurations, and the subtle differences between the 4-bank and new 8-bank DDR2 devices |
TN-47-16 |
2005-05-01T00:00:00-06:00May 2005 |
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TN-47-14: DDR2 tCKE Power-Down (both)TN-47-14: DDR2 tCKE Power-Down (both)
- Describes the tCKE timing parameter of DDR2 SDRAM |
TN-47-14 |
2004-12-01T00:00:00-07:00Dec 2004 |
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TN-47-13: DDR2 Read Interrupt (both)TN-47-13: DDR2 Read Interrupt (both)
- Describes legal execution of a READ interrupted by a READ command |
TN-47-13 |
2004-12-01T00:00:00-07:00Dec 2004 |
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TN-47-12: DDR2 Redundant DQS bothTN-47-12: DDR2 Redundant DQS both
- Describes how to enable the redundant data strobe (RDQS) |
TN-47-12 |
2004-12-01T00:00:00-07:00Dec 2004 |
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TN-47-11: DDR2 Differential DQS bothTN-47-11: DDR2 Differential DQS both
- Describes the differential DQS function of the DDR2 SDRAM |
TN-47-11 |
2004-12-01T00:00:00-07:00Dec 2004 |
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TN-47-10: DDR2 Posted CAS# Additive Latency (both)TN-47-10: DDR2 Posted CAS# Additive Latency (both)
- Describes the AL function of the DDR2 SDRAM device |
TN-47-10 |
2004-12-01T00:00:00-07:00Dec 2004 |
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TN-47-09: DDR2 SDRAM Bank Addressing (both)TN-47-09: DDR2 SDRAM Bank Addressing (both)
- Describes the evolution in array architecture from DDR to DDR2 SDRAM |
TN-47-09 |
2004-12-01T00:00:00-07:00Dec 2004 |
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TN-47-08: DDR2 Package Sizes and Layout RequirementsTN-47-08: DDR2 Package Sizes and Layout Requirements
- Covers DDR2 package sizes and layout requirements |
TN-47-08 |
2005-11-01T00:00:00-06:00Nov 2005 |
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TN-47-07: DDR2 Simulation Support TN-47-07: DDR2 Simulation Support
- Covers DDR2 simulation, adding to Micron's extensive array of design support tools for system designers |
TN-47-07 |
2004-08-01T00:00:00-06:00Aug 2004 |
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TN-47-06: Updated JEDEC DDR2 Specifications (mods too)TN-47-06: Updated JEDEC DDR2 Specifications (mods too)
- Covers the updated JEDEC specifications for systems using the initial DDR2-400 and DDR2-533 parts |
TN-47-06 |
2004-08-01T00:00:00-06:00Aug 2004 |
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TN-47-05: Power Solutions for DDR2 Notebook PCsTN-47-05: Power Solutions for DDR2 Notebook PCs
- Provides a general guideline for designing the DDR2 memory power circuitry |
TN-47-05 |
2004-06-01T00:00:00-06:00Jun 2004 |
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TN-47-04: Calculating Memory System Power for DDR2TN-47-04: Calculating Memory System Power for DDR2
- Details how DDR2 SDRAM consumes power and provides tools to estimate power consumption in a given system. |
TN-47-04 |
2006-06-01T00:00:00-06:00Jun 2006 |
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TN-47-03: DDR2 Memory Module Pinout Decode TablesTN-47-03: DDR2 Memory Module Pinout Decode Tables
- Provides sorted pin assignment tables and pin location figures for use in DDR2 DIMM signal identification, tracing, and troubleshooting |
TN-47-03 |
2004-08-01T00:00:00-06:00Aug 2004 |
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TN-47-02: DDR2 SDRAM Offers New Features and FunctionalityTN-47-02: DDR2 SDRAM Offers New Features and Functionality
- Discusses the various changes in DDR2 technology and the resulting features and benefits |
TN-47-02 |
2006-06-01T00:00:00-06:00Jun 2006 |
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TN-47-01: DDR2-533 Memory Design Guide for Two-DIMM Unbuffered SystemsTN-47-01: DDR2-533 Memory Design Guide for Two-DIMM Unbuffered Systems
- DDR2-533 memory design guide for two-DIMM, unbuffered systems |
TN-47-01 |
2004-10-01T00:00:00-06:00Oct 2004 |
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TN-46-16: 512Mb Mobile DDR: 95nm to 78nm Product Transition GuideTN-46-16: 512Mb Mobile DDR: 95nm to 78nm Product Transition Guide
- Discusses transition from 95nm to 78nm product technology |
TN-46-16 |
2007-09-01T00:00:00-06:00Sep 2007 |
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TN-46-15: Low-Power Versus Standard DDR SDRAMTN-46-15: Low-Power Versus Standard DDR SDRAM
- An overview of the functional and mechanical differences between low-power and standard DDR and a description of exclusive features of low-power DDR. |
TN-46-15 |
2007-01-01T00:00:00-07:00Jan 2007 |
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TN-46-14: Hardware Tips for Point-to-Point System DesignTN-46-14: Hardware Tips for Point-to-Point System Design
- Proven techniques for termination, layout, and routing. |
TN-46-14 |
2006-05-01T00:00:00-06:00May 2006 |
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TN-46-13: Backward Compatibility for Faster DDR SDRAMTN-46-13: Backward Compatibility for Faster DDR SDRAM
- Reviews DDR SDRAM device speed timing differences and shows the compatibility of Micron’s faster speed grade parts with its slower ones |
TN-46-13 |
2005-08-01T00:00:00-06:00Aug 2005 |
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TN-46-12: Mobile DRAM Power-Saving Features and Power CalculationsTN-46-12: Mobile DRAM Power-Saving Features and Power Calculations
- Addresses the power-saving features and power calculations of low-power Mobile DRAM memory |
TN-46-12 |
2005-10-01T00:00:00-06:00Oct 2005 |
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TN-46-11: DDR SDRAM Point-to-Point Simulation ProcessTN-46-11: DDR SDRAM Point-to-Point Simulation Process
- Covers rarely addressed areas of the DDR SDRAM point-to-point simulation process |
TN-46-11 |
2005-07-01T00:00:00-06:00Jul 2005 |
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TN-46-09: Designing for 1Gb DDR SDRAMTN-46-09: Designing for 1Gb DDR SDRAM |
TN-46-09 |
2003-12-01T00:00:00-07:00Dec 2003 |
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TN-46-08: Initialization Sequence for DDR SDRAMTN-46-08: Initialization Sequence for DDR SDRAM |
TN-46-08 |
2005-10-01T00:00:00-06:00Oct 2005 |
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TN-46-07: DDR333 Memory Design Guide for Two-DIMM Unbuffered SystemsTN-46-07: DDR333 Memory Design Guide for Two-DIMM Unbuffered Systems |
TN-46-07 |
2002-12-01T00:00:00-07:00Dec 2002 |
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TN-46-06: Termination for Point-to-Point SystemsTN-46-06: Termination for Point-to-Point Systems |
TN-46-06 |
2001-09-01T00:00:00-06:00Sep 2001 |
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TN-46-05: General DDR SDRAM FunctionalityTN-46-05: General DDR SDRAM Functionality |
TN-46-05 |
2001-07-01T00:00:00-06:00Jul 2001 |
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TN-46-04: Synchronous Timing for DDR SDRAMTN-46-04: Synchronous Timing for DDR SDRAM |
TN-46-04 |
2001-05-01T00:00:00-06:00May 2001 |
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TN-46-03: Calculating DDR Memory System PowerTN-46-03: Calculating DDR Memory System Power |
TN-46-03 |
2005-03-01T00:00:00-07:00Mar 2005 |
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TN-46-02: Decoupling Capacitor Calculation for a DDR Memory Channel TN-46-02: Decoupling Capacitor Calculation for a DDR Memory Channel |
TN-46-02 |
2004-07-01T00:00:00-06:00Jul 2004 |
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TN-45-29: Using Micron® Asynchronous PSRAM with the NXP LPC2292 and LPC2294 MicrocontrollersTN-45-29: Using Micron® Asynchronous PSRAM with the NXP LPC2292 and LPC2294 Microcontrollers
- Describes the design requirements for a seamless memory connection between the NXP LPC2292 and LPC2294 family of microcontrollers and a Micron asynchronous PSRAM device. |
TN-45-29 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-45-28: Using a Micron® CellularRAM® Device with the AMCC PPC405EZ Embedded ProcessorTN-45-28: Using a Micron® CellularRAM® Device with the AMCC PPC405EZ Embedded Processor
- Describes the design requirements for a seamless memory connection between the PPC405EZ and a Micron CellularRAM device. |
TN-45-28 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-45-27: Using Micron Asynchronous PSRAM with ADI ADSP-BF53x Blackfin® ProcessorsTN-45-27: Using Micron Asynchronous PSRAM with ADI ADSP-BF53x Blackfin® Processors
- Describes the design requirements for a seamless memory connection between Analog Device’s Blackfin® processors and Micron® 70ns, 8Mb asynchronous PSRAM devices. |
TN-45-27 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-45-25: WAIT Alignment for Micron CellularRAM DevicesTN-45-25: WAIT Alignment for Micron CellularRAM Devices
- Describes the implementation of WAIT functionality for asynchronous and burst operations |
TN-45-25 |
2007-02-01T00:00:00-07:00Feb 2007 |
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TN-45-24: Fixed-Latency Operation in CellularRAM™ 1.0 DevicesTN-45-24: Fixed-Latency Operation in CellularRAM™ 1.0 Devices
- Details how Micron has enhanced CellularRAM CR1.0 functionality |
TN-45-24 |
2006-08-01T00:00:00-06:00Aug 2006 |
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TN-45-23: Using CellularRAM Memory on a NOR FLASH BusTN-45-23: Using CellularRAM Memory on a NOR FLASH Bus
- Discusses design considerations when placing a CellularRAM memory device on a NOR Flash bus |
TN-45-23 |
2006-08-01T00:00:00-06:00Aug 2006 |
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TN-45-22: Variable vs. Fixed Latency CellularRAM™ OperationTN-45-22: Variable vs. Fixed Latency CellularRAM™ Operation
- This technical note assists designers in understanding the differences between CellularRAM variable and fixed latency operations. |
TN-45-22 |
2006-08-01T00:00:00-06:00Aug 2006 |
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TN-45-20: Low-Power Options for Async/Page CellularRAM TN-45-20: Low-Power Options for Async/Page CellularRAM
- Discusses the low-power options available to customers on async/page CellularRAM memory devices |
TN-45-20 |
2006-05-01T00:00:00-06:00May 2006 |
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TN-45-18: Using CellularRAM® Memory to Replace NEC Mobile Specified RAM (µPD46128512)TN-45-18: Using CellularRAM® Memory to Replace NEC Mobile Specified RAM (µPD46128512)
- Discusses migrating a 128Mb NEC Mobile Specified RAM design (µPD46128512) to Micron 128Mb CellularRAM memory (MT45W8MW16B). Both hardware and software changes are covered. |
TN-45-18 |
2006-03-01T00:00:00-07:00Mar 2006 |
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TN-45-17: Using CellularRAM® Memory to Replace Single- and Dual-Chip Select SRAMTN-45-17: Using CellularRAM® Memory to Replace Single- and Dual-Chip Select SRAM
- Discusses migrating a single- or dual-chip select SRAM design to Micron® CellularRAM® memory. Both hardware and software changes are covered. |
TN-45-17 |
2007-01-01T00:00:00-07:00Jan 2007 |
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TN-45-16: Using CellularRAM Memory to Replace Fujitsu 1.8V FCRAMTN-45-16: Using CellularRAM Memory to Replace Fujitsu 1.8V FCRAM
- Discusses replacing Fujitsu 1.8V FCRAM with Micron CellularRAM memory |
TN-45-16 |
2006-03-01T00:00:00-07:00Mar 2006 |
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TN-45-15: Row Boundary Crossing Functionality in CellularRAM™ MemoryTN-45-15: Row Boundary Crossing Functionality in CellularRAM™ Memory
- Explains row boundary crossing in Micron CellularRAM memory devices |
TN-45-15 |
2007-09-01T00:00:00-06:00Sep 2007 |
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TN-45-14: Using CellularRAM Memory to Replace Fujitsu 3V FCRAMTN-45-14: Using CellularRAM Memory to Replace Fujitsu 3V FCRAM
- Discusses replacing Fujitsu 3V FCRAM with Micron CellularRAM memory |
TN-45-14 |
2006-03-01T00:00:00-07:00Mar 2006 |
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TN-45-13: Using CellularRAM Memory to Replace UtRAMTN-45-13: Using CellularRAM Memory to Replace UtRAM
- Assists migration from a 128Mb UtRAM design (K1B2816B6M) to Micron 128Mb CellularRAM memory (MT45W8MW16B). Both hardware and software changes are covered. |
TN-45-13 |
2006-02-01T00:00:00-07:00Feb 2006 |
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TN-45-10: Designing Applications with the x16 Burst A/D Multiplexed InterfaceTN-45-10: Designing Applications with the x16 Burst A/D Multiplexed Interface
- Discusses the differences between a burst non-A/D MUX and burst A/D MUX device |
TN-45-10 |
2005-01-01T00:00:00-07:00Jan 2005 |
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TN-45-09: 64Mb Burst CellularRAM P25A to P25Z Transition GuideTN-45-09: 64Mb Burst CellularRAM P25A to P25Z Transition Guide
- Discusses migrating a design based on the async/page/burst MT45W4MW16B (P25A) to MT45W4MW16BC (P25Z) |
TN-45-09 |
2005-01-01T00:00:00-07:00Jan 2005 |
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TN-45-08: 64Mb Async/Page CellularRAM P25A to P25Z Transition GuideTN-45-08: 64Mb Async/Page CellularRAM P25A to P25Z Transition Guide
- Discusses migrating a design based on the async/page MT45W4MW16P (P25A) to the MT45W4MW16PC (P25Z) |
TN-45-08 |
2005-01-01T00:00:00-07:00Jan 2005 |
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TN-45-07: Implementing CellularRAM® 2.0 x32 with Two CellularRAM 1.5 x16 DevicesTN-45-07: Implementing CellularRAM® 2.0 x32 with Two CellularRAM 1.5 x16 Devices
- Documents how the x32 CR2.0 memory interface can be emulated using a two-die stack of x16 CR 1.5 devices. |
TN-45-07 |
2007-03-01T00:00:00-07:00Mar 2007 |
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TN-45-06: Density Migration for x16 Burst Multiplexed PSRAM IntroductionTN-45-06: Density Migration for x16 Burst Multiplexed PSRAM Introduction
- Discusses the design differences to account for when migrating a burst multiplexed device from 16Mb to 64Mb |
TN-45-06 |
2006-01-01T00:00:00-07:00Jan 2006 |
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TN-45-04: CellularRAM Multiplexed Async/Burst OperationTN-45-04: CellularRAM Multiplexed Async/Burst Operation
- Discusses multiplexing a non-multiplexed CellularRAM device at the substrate level |
TN-45-04 |
2005-03-01T00:00:00-07:00Mar 2005 |
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TN-45-02: CellularRAM Asynchronous and Mixed-Mode Slow-Clock WRITE ConcernsTN-45-02: CellularRAM Asynchronous and Mixed-Mode Slow-Clock WRITE Concerns
- Discusses the use of Micron CellularRAM-based devices in Mixed Mode operation and slow clock speeds |
TN-45-02 |
2005-09-01T00:00:00-06:00Sep 2005 |
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TN-45-01: Functional Differences Between CellularRAM 1.0 and CellularRAM 1.5TN-45-01: Functional Differences Between CellularRAM 1.0 and CellularRAM 1.5
- Discusses the functional difference between the CellularRAM 1.0 and CellularRAM 1.5 memory devices |
TN-45-01 |
2005-08-01T00:00:00-06:00Aug 2005 |
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DDR3 Termination Data StrobeDDR3 Termination Data Strobe
- Provides guidelines for using the TDQS feature to reduce signal integrity issues associated with mismatched DQS loading in in combined x4-based/x8-based systems |
TN-41-06 |
2008-03-01T00:00:00-07:00Mar 2008 |
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TN-41-04: DDR3 Dynamic On-Die TerminationTN-41-04: DDR3 Dynamic On-Die Termination
- With DDR3, dynamic ODT provides systems with increased flexibility to optimize termination values for different loading conditions. |
TN-41-04_PDF |
2008-03-01T00:00:00-07:00Mar 2008 |
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TN-41-02: DDR3 ZQ CalibrationTN-41-02: DDR3 ZQ Calibration
- Describes how the DDR3 SDRAM driver design has been enhanced |
TN-41-02 |
2008-02-01T00:00:00-07:00Feb 2008 |
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Calculating Memory System Power For DDR3Calculating Memory System Power For DDR3
- Details how DDR3 SDRAM consumes power and provides the tools that system designers can use to estimate power consumption. |
TN-41-01 |
2007-08-01T00:00:00-06:00Aug 2007 |
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TN-29-28: Memory Management in NAND Flash ArraysTN-29-28: Memory Management in NAND Flash Arrays
- Describes common NAND Flash memory-management methods for effective use of the NAND Flash memory array. |
TN-29-28 |
2007-07-01T00:00:00-06:00Jul 2007 |
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TN-29-26: NAND Flash Status Register Response in Cache Programming OperationsTN-29-26: NAND Flash Status Register Response in Cache Programming Operations
- Describes status register responses when operating in cache programming modes. |
TN-29-26 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-25: Improving NAND Flash Performance Using Two-Plane Command Enabled Micron DevicesTN-29-25: Improving NAND Flash Performance Using Two-Plane Command Enabled Micron Devices
- Describes the performance benefits of Micron two-plane commands, and provides implementation guidelines for making the best use of two-plane capabilities. |
TN-29-25 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-24: Micron Wire-Bonding TechniquesTN-29-24: Micron Wire-Bonding Techniques |
TN-29-24 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-19: NAND Flash 101 - An Introduction to NAND Flash and How to Design It In to Your Next ProductTN-29-19: NAND Flash 101 - An Introduction to NAND Flash and How to Design It In to Your Next Product |
TN-29-19 |
2006-11-01T00:00:00-06:00Nov 2006 |
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TN-29-18: Booting from Embedded MMCTN-29-18: Booting from Embedded MMC
- Describes booting from an embedded ARM processor in the MMC environment. |
TN-29-18 |
2007-10-01T00:00:00-06:00Oct 2007 |
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TN-29-17: NAND Flash Design and Use ConsiderationsTN-29-17: NAND Flash Design and Use Considerations
- Describes design and use considerations for NAND Flash memory, focusing on bad-block identification and error correction. |
TN-29-17 |
2006-08-01T00:00:00-06:00Aug 2006 |
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TN-29-16: Boot-from-NAND Using Micron MT28F1G08ABA NAND Flash with the Texas Instruments™ OMAP™ 2420 ProcessorTN-29-16: Boot-from-NAND Using Micron MT28F1G08ABA NAND Flash with the Texas Instruments™ OMAP™ 2420 Processor |
TN-29-16 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-15: NAND Flash Performance Improvement Using Internal Data MoveTN-29-15: NAND Flash Performance Improvement Using Internal Data Move
- NAND data management capabilities and higher system performance through NAND Flash internal data moves |
TN-29-15 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-14: NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE CommandTN-29-14: NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command |
TN-29-14 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-13: Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash DevicesTN-29-13: Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash Devices |
TN-29-13 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-11: NAND Flash SecurityTN-29-11: NAND Flash Security |
TN-29-11 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-10: Freescale™ DragonBall™ MX1 Adaptation for NAND Flash MemoryTN-29-10: Freescale™ DragonBall™ MX1 Adaptation for NAND Flash Memory |
TN-29-10 |
2007-06-01T00:00:00-06:00Jun 2007 |
Download NAND Low Level Flash Drivers |
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TN-29-08: Hamming Codes for NAND Flash MemoriesTN-29-08: Hamming Codes for NAND Flash Memories |
TN-29-08 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-07: Small Block vs. Large Block NAND DevicesTN-29-07: Small Block vs. Large Block NAND Devices |
TN-29-07 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-06: Micron NAND Flash Controller via Xilinx Spartan-3 FPGATN-29-06: Micron NAND Flash Controller via Xilinx Spartan-3 FPGA |
TN-29-06 |
2005-04-01T00:00:00-06:00Apr 2005 |
Download VHDL Code |
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TN-29-05: Micron ECC Module for NAND Flash via Xilinx™ Spartan™-3 FPGATN-29-05: Micron ECC Module for NAND Flash via Xilinx™ Spartan™-3 FPGA |
TN-29-05 |
2007-06-01T00:00:00-06:00Jun 2007 |
Download VHDL Code |
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TN-29-04: Using Micron MT29F2G08AACWP NAND Flash Memory in 2Gb Samsung K9F2G08U0A ApplicationsTN-29-04: Using Micron MT29F2G08AACWP NAND Flash Memory in 2Gb Samsung K9F2G08U0A Applications |
TN-29-04 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-03: Using Micron MT29F2G08AACWP NAND Flash Memory in Toshiba TC58NVG1S3BTG00 ApplicationsTN-29-03: Using Micron MT29F2G08AACWP NAND Flash Memory in Toshiba TC58NVG1S3BTG00 Applications |
TN-29-03 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-29-01: NAND Flash Performance Increase - Using the Micron® PAGE READ CACHE MODE CommandTN-29-01: NAND Flash Performance Increase - Using the Micron® PAGE READ CACHE MODE Command |
TN-29-01 |
2007-06-01T00:00:00-06:00Jun 2007 |
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TN-04-52: Sourcing Micron Memory Modules for the Intel 865 (Springdale) and 875 (Canterwood) Series Chipsets TN-04-52: Sourcing Micron Memory Modules for the Intel 865 (Springdale) and 875 (Canterwood) Series Chipsets
- Discusses two important functional differences between the 865 and 875 to consider when sourcing memory modules |
TN-04-52 |
2003-08-01T00:00:00-06:00Aug 2003 |
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TN-04-49: Comparing Module ParametersTN-04-49: Comparing Module Parameters |
TN-04-49 |
2003-01-01T00:00:00-07:00Jan 2003 |
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TN-04-47: Choosing The Correct 168-Pin DIMM SocketTN-04-47: Choosing The Correct 168-Pin DIMM Socket
- Assists designers in selecting the correct 168-pin DIMM socket for any application |
TN-04-47 |
1999-11-01T00:00:00-06:00Nov 1999 |
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TN-04-44: Maximizing DRAM Valid Data-Out WindowTN-04-44: Maximizing DRAM Valid Data-Out Window
- Explains how to maximize the SDRAM valid data-out window |
TN-04-44 |
1999-02-01T00:00:00-07:00Feb 1999 |
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TN-04-42: Memory Module Serial Presence-DetectTN-04-42: Memory Module Serial Presence-Detect
- Focuses on SPD values and definitions for DDR memory |
TN-04-42 |
2003-10-01T00:00:00-06:00Oct 2003 |
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TN-04-30: Various Methods of DRAM RefreshTN-04-30: Various Methods of DRAM Refresh
- Addresses frequently asked questions about DRAM refresh |
TN-04-30 |
1999-02-01T00:00:00-07:00Feb 1999 |
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TN-00-21: SEMI-Defined Wafer Map Format IntroductionTN-00-21: SEMI-Defined Wafer Map Format Introduction |
TN-00-21 |
2007-10-01T00:00:00-06:00Oct 2007 |
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TN-00-20: The Value of Signal IntegrityTN-00-20: The Value of Signal Integrity
- Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life |
TN-00-20 |
2005-06-01T00:00:00-06:00Jun 2005 |
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TN-00-19: Thinning Considerations for Wafer ProductsTN-00-19: Thinning Considerations for Wafer Products
- Information on optimal wafer-thinning processes to meet specific customer requirements |
TN-00-19 |
2004-11-01T00:00:00-06:00Nov 2004 |
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TN-00-18: Uprating of Semiconductors for High-Temperature ApplicationsTN-00-18: Uprating of Semiconductors for High-Temperature Applications
- Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer’s environmental specifications |
TN-00-18 |
2007-02-01T00:00:00-07:00Feb 2007 |
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TN-00-17: Timing Specification Derating for High Capacitance Output LoadingTN-00-17: Timing Specification Derating for High Capacitance Output Loading
- Describes how to create capacitance derating data for Micron products that can then be used in preliminary evaluations of system timing |
TN-00-17 |
2004-05-01T00:00:00-06:00May 2004 |
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TN-00-16: Singulated Die Shipping MediaTN-00-16: Singulated Die Shipping Media |
TN-00-16 |
2004-02-01T00:00:00-07:00Feb 2004 |
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TN-00-15: Recommended Soldering ParametersTN-00-15: Recommended Soldering Parameters |
TN-00-15 |
2007-03-01T00:00:00-07:00Mar 2007 |
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TN-00-14: Understanding the Quality and Reliability Requirements for Bare Die ApplicationsTN-00-14: Understanding the Quality and Reliability Requirements for Bare Die Applications |
TN-00-14 |
2001-09-01T00:00:00-06:00Sep 2001 |
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TN-00-09: Accelerate Design Cycles With Micron Simulation ModelsTN-00-09: Accelerate Design Cycles With Micron Simulation Models |
TN-00-09 |
2006-10-01T00:00:00-06:00Oct 2006 |
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TN-00-08: Thermal ApplicationsTN-00-08: Thermal Applications
- Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature. |
TN-00-08 |
2007-02-01T00:00:00-07:00Feb 2007 |
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TN-00-07: IBIS Behavioral ModelsTN-00-07: IBIS Behavioral Models |
TN-00-07 |
1999-09-01T00:00:00-06:00Sep 1999 |
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TN-00-06: Bypass Capacitor Selection for High-Speed DesignsTN-00-06: Bypass Capacitor Selection for High-Speed Designs |
TN-00-06 |
1999-09-01T00:00:00-06:00Sep 1999 |
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TN-00-01: Moisture Absorption in Plastic PackagesTN-00-01: Moisture Absorption in Plastic Packages
- Describes the shipping procedures that ensure Micron’s customers receive memory devices that do not exhibit the popcorn effect |
TN-00-01 |
2007-03-01T00:00:00-07:00Mar 2007 |
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184-pin DDR RDIMM JEDEC Design Standard184-pin DDR RDIMM JEDEC Design Standard
- This specification defines the electrical and mechanical requirements for 184-pin, 2.5V, PC1600/PC2100, 64/72-bit wide, DDR SDRAM RDIMMs. |
JEDEC TN-03 |
2006-05-01T00:00:00-06:00May 2006 |
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SPD JEDEC Standards for UDIMMs, RDIMMs, and SODIMMsSPD JEDEC Standards for UDIMMs, RDIMMs, and SODIMMs
- This application note fully describes the Serial Presence Detect assignments for SPD used on DDR SDRAM Modules |
JEDEC TN-02 |
2001-11-01T00:00:00-06:00Nov 2001 |
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JEDEC 184-pin DDR RDIMM JEDEC Mechanical DimensionsJEDEC 184-pin DDR RDIMM JEDEC Mechanical Dimensions |
JEDEC TN-01 |
1998-08-01T00:00:00-06:00Aug 1998 |
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