Home > Design Support > Part Information > DDR Toolbox > Unbuffered DIMM Design Files and Configurations

Unbuffered DIMM Design Files and Configurations

print this page
Design Support

DDR Unbuffered DIMM Design Files and Configurations

Notice: Module builds should be done using the current Gerber release. The "Proposed Specification Changes and Additions" highlighted on this Web site are for information purposes only and should not be implemented in PCB builds until the changes are incorporated into the corresponding design release.

Raw Card Version

DIMM Capacity

DIMM Organization

SDRAM Density

SDRAM Organization

# SDRAMs

# Banks (DIMM)

Address Bits row/col/banks

A0

Raw Card A is a single-bank, single-sided PCB for use with x8 DDR SDRAM components. It has the advantage over the Raw Card B "depopulated" single-bank in that it will be a single-pass assembly (all components are on a single-side of the PCB). In addition to the cost-saving potential, the reason for a specific single-bank design is to improve address/command bus arrival time skews between different module mixes. This will improve system timing budget margins.

 

64MB   8 Meg x 64 64Mb   8 Meg x 8 8 1 12/9/2
128MB 16 Meg x 64 128Mb 16 Meg x 8 8 1 12/10/2
256MB 32 Meg x 64 256Mb 32 Meg x 8 8 1 13/10/2
512MB 64 Meg x 64 512Mb 64 Meg x 8 8 1 13/11/2
64MB + ECC   8 Meg x 72 64Mb   8 Meg x 8 9 1 12/9/2
128MB + ECC 16 Meg x 72 128Mb 16 Meg x 8 9 1 12/10/2
256MB + ECC 32 Meg x 72 256Mb 32 Meg x 8 9 1 13/10/2
512MB + ECC 64 Meg x 72 512Mb 64 Meg x 8 9 1 13/11/2

Raw Card Version

DIMM Capacity

DIMM Organization

SDRAM Density

SDRAM Organization

# SDRAMs

# Banks (DIMM)

Address Bits row/col/banks

B1

Project: Unbuffered Raw Card B (x8-based dual-bank x64/x72)

Released Version B0 - Changes for revision (B1), released in March 2000

  • Fine-tuned clock lines to tighten skew.Lengths matched to 1mil
  • Fine-tuned clock lines to reduce or remove low grade crosstalk
  • Fine-tuned data nets to matched length tolerance of 1mil
  • Modified outline_pg1.ps drawing to allow component placement above end notches according to JEDECstandards
  • Converted VREF to VDD bypass to VREF to VSS
  • Changed C22 to a VREF to VSS bypass
  • Increased trace widths on all VDD and VSS traces
  • Changed via pad size to 0.022" and antipad size to 0.032"
  • Removed EEPROM WP signal
64MB   8 Meg x 64 64Mb   8 Meg x 8 8 1* 12/9/2
128MB 16 Meg x 64 128Mb 16 Meg x 8 8 1* 12/10/2
256MB 32 Meg x 64 256Mb 32 Meg x 8 8 1* 13/10/2
512MB 64 Meg x 64 512Mb 64 Meg x 8 8 1* 13/11/2
64MB + ECC   8 Meg x 72 64Mb   8 Meg x 8 9 1* 12/9/2
128MB + ECC 16 Meg x 72 128Mb 16 Meg x 8 9 1* 12/10/2
256MB + ECC 32 Meg x 72 256Mb 32 Meg x 8 9 1* 13/10/2
512MB + ECC 64 Meg x 72 512Mb 64 Meg x 8 9 1* 13/11/2
128MB 16 Meg x 64 64Mb   8 Meg x 8 16 2 12/9/2
256MB 32 Meg x 64 128Mb 16 Meg x 8 16 2 12/10/2
512MB 64 Meg x 64 256Mb 32 Meg x 8 16 2 13/10/2
1GB 128 Meg x 64 512Mb 64 Meg x 8 16 2 13/11/2
128MB + ECC 16 Meg x 72 64Mb   8 Meg x 8 18 2 12/9/2
256MB + ECC 32 Meg x 72 128Mb 16 Meg x 8 18 2 12/10/2
512MB + ECC 64 Meg x 72 256Mb 32 Meg x 8 18 2 13/10/2
1GB + ECC 128 Meg x 72 512Mb 64 Meg x 8 18 2 13/11/2

Raw Card Version

DIMM Capacity

DIMM Organization

SDRAM Density

SDRAM Organization

# SDRAMs

# Banks (DIMM)

Address Bits row/col/banks

C2

Implemented: Unbuffered Raw Card C2

This release added series stub resistors for the C/A signals and incorporated design changes based on feedback and hardware analysis of Raw Card C1

  • Added 7.5 ohm series resistors to command and address signals*
  • Added copper fill to unrouted areas on the signal layers
  • Added four SDRAM decoupling caps
  • Added a VDDSPD decoupling cap and increased trace width
  • Moved DQS traces from L3 and L4 to the secondary side for consistency

* Note: This is a long leadtime item. One supplier currently tooling this pack is Bourns--part number: CAY10-7R40F2

32MB   4 Meg x 64 64Mb   4 Meg x 16 4 1 12/8/2
64MB   8 Meg x 64 128Mb   8 Meg x 16 4 1 12/9/2
128MB 16 Meg x 64 256Mb 16 Meg x 16 4 1 13/9/2
256MB 32 Meg x 64 512Mb 32 Meg x 16 4 1 13/10/2
32MB + ECC   4 Meg x 72 64Mb   4 Meg x 16 5 1 12/8/2
64MB + ECC   8 Meg x 72 128Mb   8 Meg x 16 5 1 12/9/2
128MB + ECC 16 Meg x 72 256Mb 16 Meg x 16 5 1 13/9/2
256MB + ECC 32 Meg x 72 512Mb 32 Meg x 16 5 1 13/10/2

 

Previous Revisions B0 C0 C1

* Raw Card B may be depopulated to a single-bank DIMM; however, it is recommended (and encouraged) that Raw Card A be used for single-bank, x8-based DIMMs.