Are Verilog models available for Micron modules?
Verilog models can be created for DDR, DDR2, and DDR3 modules by using a Micron-provided wrapper in conjunction with the Verilog model for the DRAM components used on the specific module you're working with. The configurable DIMM model file (ddr_dimm.v, ddr2_module.v, or ddr3_dimm.v) is included in the DRAM Verilog model .zip file download for DDR, DDR2, and DDR3 components.
The readme.txt file included in the .zip provides instructions for configuring the DIMM model.
Can a parity module be used in a system that is not designed to use parity?
Micron’s modules are manufactured to be hardware-compatible with both parity and non-parity systems.
Par_in (parity in) and the high order address signals have a weak (100K-ohm) pull-down resistor to stabilize the inputs from oscillating around the switch point.
Err_out (parity error out) is an open drain and should be left as a true no connect unless used in a parity system.
The SPD data on a parity module does reflect parity. In rare occasions, the firmware or BIOS of a non-parity system will err on the parity bit in the SPD. For this reason, the system designer should ensure that the firmware of the non-parity system expects or ignores this portion of the SPD data.
Can Micron provide models for the module connectors?
It is suggested that models for connectors be acquired from the connector manufacturers to ensure an accurate model. Micron may be able to provide a simple, uncoupled RLC connector model to be used as is or to create your own connector model. Please e-mail DRAM Support
to request this model.
Can Micron provide module Gerber files to customers?
As a rule, Gerber and ODB++ files are not provided to customers, because the files contain proprietary information about our design and could be used to mass-produce our product without our consent.
There is normally no reason that a customer would need Gerber files. Gerber files are provided to PCB manufacturers to mass-produce PCBs. IBIS, EBD, or board files provide enough information for customers to create models and perform signal integrity simulations.
Does Micron provide Hyperlynx models?
Micron can provide Hyperlynx models upon request for most modules. Please e-mail DRAM Support
with your request and provide the complete part number of the module you are interested in. Please note, it may take up to two weeks to receive the model once your request has been acknowledged.
Does Micron provide VHDL models for modules?
Micron does not provide VHDL models for modules. We have focused our modeling resources on higher utilized modeling standards such as IBIS, Verilog, and HSPICE.
However, alternatives to VHDL models are available:
Denali and Synopsys both have libraries of memory components and module models available on their
Web sites. These EDA packages may be an alternate way to create behavioral simulations in the absence of VHDL model.
Some simulators such as ModelSim provide a dual language option (VHDL and Verilog). To simulate in this manner, a VHDL wrapper can be used around currently available Verilog models.
Does the model that I'm downloading support all the drive strengths listed in the data sheet?
To discover the model’s supported drive strengths, do the following:
- HSPICE model: Look at the .sp files for information on supported drive strengths and how to select them.
- IBIS model: Do a text search for the [Model Selector] section. This section describes the drive strengths that can be selected for a given input/output or output buffer.
How do I tell if I have the correct IBIS or HSPICE model for a given die revision indicator?
HSPICE model: Look in the readme file for die revision information.
IBIS model: Look at the top of the file for die revision information.
How does Micron validate the quality of its IBIS and HSPICE models?
To validate a model to lab measurements, Micron compares several items, such as input capacitance, power and ground clamp diode characteristics, output buffer drive strength, and output buffer slew rates. New Micron models include a quality report that compares model characteristics to lab measurements and data sheet specifications.
My simulation software does not support IBIS 4.0 and newer standards. How do I make Micron's IBIS 4.0 level model work with my IBIS 3.2-compliant simulator?
Most Micron models contain very few keywords specific to IBIS 4.0. In many cases, the model can be made IBIS 3.2-compliant with a few simple changes. First, change the [IBIS Ver] keyword to 3.2. Next, place a comment character ("|") in front of the "Vref" section under each [Model Spec] keyword. Finally, comment out each [Receiver Thresholds] section.
What advantage do dual-rank modules have over single-rank modules?
Having 2 ranks available to the memory controller is advantageous in terms of both performance and power. For example, while the controller is waiting for a 64-bit word to be available on one rank, the second 64-bit rank can be accessed. This interleaving increases the overall performance of the module. Power can also be reduced on a rank that is not in use, reducing the power consumption of the module.
What does the model revision number indicate when it changes from a 1.x level to a 2.x level?
1.x level model indicates that the model has not been correlated to any lab measurements. Typically, 1.x level models are provided for pre-silicon or pre-production devices. A 2.x level model has been correlated to lab measurements.
What is a board (.brd) file?
A board file is a complete electrical and mechanical representation of a PCB. EBD and ODB++ files are generated from board files. Board files are not to be provided to customers without an NDA since the files contain confidential and proprietary information about the module design.
What is a Gerber file?
Gerbers are files sent to PCB manufacturers to produce PCBs. Gerber is a dated term because board shops currently require ODB++ files to mass-produce PCBs. The term Gerber is used loosely. It sometimes refers to any of the files that represent the PCB’s electrical and mechanical characteristics, including EBD, ODB++, and board files. When a customer asks for Gerber files for a module, it is important to determine what specific files they really need.
What is a "rank"?
A rank typically refers to the data bus width of a system. This width is generally 64 or 72 bits. For example, if 8 components with a width of 8 bits each are mounted to a PCB, this creates a module that is 64 bits wide, enabling a 64-bit word to be read out of the module. We refer to this as a "single-rank" module. Sixteen components with a width of 8 bits each can be mounted to a PCB to form two, 64-bit-wide ranks, creating a "dual-rank" module.
What is an EBD (.ebd) file?
An EBD file is a model of a PCB used for simulations. This file describes the electrical characteristics of the pins and traces on the PCB. An EBD file used in conjunction with IBIS models of the DRAM, registers, and PLL can be used to create a model of a module.
What is an IBIS (.ibs) file?
An .ibs or IBIS file is a representation of a circuit meant to be read by a simulation application such as Cadence® Allegro® or HyperLynx®. IBIS (Input/output Buffer Information Specification) is an EIA (Electronic Industries Alliance) standard. IBIS is a text file in a specific format that represents the current versus voltage and voltage vs. time characteristics of the inputs and outputs of a circuit. IBIS models are the preferred files to provide to customers since the files do not contain any proprietary information about the internal makeup of the components. NDAs are not normally required for IBIS files.
What is the advantage of multiple banks within a component?
Memory controllers can begin an operation in one bank and perform a separate operation in a different bank while the first operation is completing. This interleaving increases the performance of the DRAM as a whole.
What is the difference between a "bank" and a "rank?"
Banks are specific to individual DRAM components and refer to sub-arrays within the DRAM component. Ranks are specific to memory modules and refer to a sub-array made of multiple DRAM components.
What makes up an IBIS model for a module?
The complete IBIS model for a module consists of several files:
1. The IBIS models of the DRAM used on that particular module
2. The IBIS models of the PLL, registers, and EEPROMs (as needed)
3. The IBIS model of the resistive parallel terminations on the PC
4. The EBD (electronic board description) file of the PCB. This file references the IBIS file of the terminations mentioned above.
Together, these files provide a complete representation of the PCB.
What trace lengths and termination values does Micron suggest I use on my memory interface?
Board designers often ask this question when they’re looking for a starting point for their CAD drawings or simulations. Because there are so many variables to consider, it is difficult to provide a "correct" answer. Clock speed, 1T or 2T timing, registered or unbuffered modules, and trace impedance are all important factors. Some controllers have on-die termination, some do not. Some controllers have two copies of the command and address bus. All of these factors can affect trace lengths and termination and can affect how acceptable signal integrity is achieved.
Micron technical notes TN-47-01
, and TN-46-14
can be used as a starting point, but trace length and termination must ultimately be proven by simulation and physical testing. Micron provides an online simulator for customers who do not have the expertise or resources to run simulations. The online simulator is on a secure section of Micron.com; visit the following URL to request access: www.micron.com/simulators
Why are IBIS models for DRAM components regularly posted to micron.com but not IBIS models for modules?
We have found that it is more efficient to create module models as they are requested by our customers. If you are unable to locate the IBIS model for the module you are interested in, please e-mail your request to DRAM Support