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Kick Your Data Into High Gear

Watch the industry's first interoperability demonstration between Altera Stratix V FPGAs and Micron's Hybrid Memory Cube.

Our short-reach (SR) Hybrid Memory Cube (HMC) SERDES PHY form factor provides data throughput unlike any other memory device on the market today. It’s designed for systems that use standard FBGA packaging and is an ideal point-to-point memory solution for ASIC, CPU, and ASSP devices.

Our SR HMC is available in two package sizes. The 31mm x 31mm package provides full 160 GB/s bandwidth. The 16mm x 19.5mm package is available for designs requiring a smaller form factor and is optimal for systems using less-than-full bandwidth.

Density Interface Voltage Package Op. Temp.

2GB

See 2 Products
15G SR 1.2V BGA, FBGA 0C to +95C

4GB

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15G SR 1.2V BGA, FBGA 0C to +95C
Topics Relating to Hybrid Memory Cube
Networking Solutions

Networking Innovations

We’re addressing the mobility revolution with new memory solutions that deliver revolutionary results for networking applications.

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Supercomputing Memory

Supercomputing Memory

We offer best-in-class solutions that deliver power efficiency, performance, and reliability for critical workloads.

   Learn more about Supercomputing Memory

  • Increased Bandwidth – Provides up to 15X the bandwidth of a DDR3 module
  • Reduced Power – Uses up to 70% less energy per bit than DDR3-1333
  • Smaller Size – Reduces the memory footprint by nearly 90% compared to today’s RDIMMs due to HMC’s stacked architecture
  • Scalable – Includes logic layer flexibility, which enables HMC to be tailored to multiple platforms and applications
  • Reduced Latency – Enables significantly lower system latency as a result of HMC’s massive parallelism
  • Ultra Reliability – Delivers greater resilience and field reparability with a new paradigm of system-level, advanced reliability, availability, and serviceability (RAS) features that include embedded error checking and correction capabilities
  • Abstracted Memory – Enables designers to leverage HMC’s revolutionary features and performance without having to interface with complex memory parameters; manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation
  • Low Total Cost of Ownership (TCO) – Lowers TCO thanks to HMC’s high performance, low energy, and RAS capabilities

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All About HMC

Hybrid Memory Cube

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Hybrid Memory Cube Gains Traction

The Much Anticipated Physical Roll-out of Micron's Hybrid Memory Cube at the annual Supercomputing Conference.

Supercomputing Memory

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For Short-Reach HMC (4)
Title & Description Secure ID# Updated Type
HMC Thermal Management: (PDF 327.66 KB) This technical note provides guidance on developing thermal system solutions that meet HMC's operational temperature specifications. TN-43-05 02/2014 Technical Note
Short-Reach Hybrid Memory Cube PDN Requirements: (PDF 5.3 MB) This technical note discusses the power delivery network (PDN) requirements of the SR HMC form factor. TN-43-04 10/2013 Technical Note
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
HMC: Setting the Bar for Reliability, Availability, and Serviceability (RAS): (PDF 722.78 KB)Discusses how Micron’s HMC resolves the inherent problems regarding the reliability of DRAM and the industry trends to compensate for the issues. 05/2013 White Paper
For Hybrid Memory Cube (1)
Title & Description Secure ID# Updated Type
HMC Part Numbering System: (PDF 58.88 KB)Part numbering guide for Hybrid Memory Cube 01/2014 Part Numbering Guide
For Products and Support (14)
Title & Description Secure ID# Updated Type
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Product Marks/Product and Packaging Labels: (PDF 1.39 MB)Explains product part marking, and product and packaging labels. CSN-11 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron Component and Module Packaging: (PDF 1.41 MB)Explanation of Micron packaging labels and procedures. CSN-16 01/2013 Customer Service Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

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Short-Reach HMC FAQs (3)

How do I access a data sheet or technical information for Micron’s HMC parts?

HMC technical documents—including the datasheet—are only available under a non-disclosure agreement (NDA).  Please work with your sales representative for access.

What Micron parts are available?

Our 2GB HMC device composed of a stack of four 4Gb DRAM die is available.   HMC is designed using the HMCC’s short-reach (SR) PHY definition and is available in two package sizes. The 31mm x 31mm package offers four links with full 160 GB/s bandwidth. The smaller 16mm x 19.5mm package offers two links with 120 GB/s of bandwidth; it is optimal for systems requiring a smaller form factor and less-than-full bandwidth. Micron will be sampling a 4GB SR device in early 2014.

When is Micron planning for HMC volume production?

2014.

Hybrid Memory Cube FAQs (10)

Where can the HMCC specification be accessed?

The HMCC specification is publically available on hybridmemorycube.org.

What is the HMCC and what are its goals?

The Hybrid Memory Cube Consortium (HMCC) is a working group made up of industry leaders who build, design in, or enable HMC technology. The goal of the HMCC is to define industry-adoptable HMC interfaces and to facilitate the integration of HMC into a wide variety of applications that enable developers, manufacturers, and enablers to leverage this revolutionary technology.

What industries/segments do you anticipate will be affected the most?

Any applications where high performance and energy efficiency are critical will be dramatically affected by this technology. For example, the challenge for network systems to maintain line speed performance provides an excellent opportunity for HMC. System developers recognize that a memory bottleneck exists for system development beyond 100Gb and are actively looking for high-performance memory applications for data packet processing and data packet buffering or storage.

The high-performance computing segment is also hitting the memory wall. While processor roadmaps attempt to keep pace through core and thread doubling, core and thread count has not been matched with adequate memory performance. The second major challenge for high-performance computing is energy consumption. Higher-performance processing and exponential bit growth requirements are pushing data centers beyond practical limits for managing power and total cost of ownership. A more energy-efficient solution is desperately needed.
What makes HMC so different?

With performance levels that break through the memory wall, HMC unlocks a myriad of  system performance advancements for the next generation of high-performance computing and advances network capabilities to support 100Gb and 400Gb system development.

HMC represents a fundamental change in memory construction and connectivity. Utilizing advanced 3D interconnect technology, HMC blends the best of logic and DRAM processes into a heterogeneous package. The foundation of HMC is a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon-via (TSV) bonds. An energy-optimized DRAM array provides efficient access to memory bits via the logic layer, creating an intelligent memory device that’s truly optimized for performance and energy efficiencies. This elemental change in how memory is built into a system is paramount. By placing intelligent memory on the same substrate as the logic, each part of the system can function as it’s designed more efficiently than with previous technologies.

Why are current DRAM technologies unable to fully solve this problem?

Current memory technology roadmaps do not provide sufficient performance to optimally meet the CPU, GPU, and ASIC memory bandwidth requirements. By advancing past the traditional DRAM architecture, HMC is establishing a new standard of memory to match the advancements of CPU, GPU and ASIC roadmaps. HMC offers system designers optimum flexibility in developing next-generation system architecture.

What problem does HMC solve?

Over time, memory bandwidth has become a severe bottleneck to optimal system performance. Conventional memory technologies are not scaling with Moore’s Law; therefore, they are not keeping pace with the increasing performance demands of the latest microprocessor and application-specific integrated circuit (ASIC) roadmaps. Microprocessor and ASIC enablers are doubling cores and threads per core to greatly increase performance and workload capabilities. They are doing this by distributing work sets into smaller blocks among an increasing number of work elements (cores). Multiple compute elements per processor require an increasing amount of memory accesses per element. The term “memory wall” has been used to describe this dilemma. With performance levels that break through the memory wall, HMC is a revolutionary technology that enables greater performance for next-generation computing and high-speed networking systems.

What are challenges of HMC implementation?

As with any leading technology, some of the “copy and paste” aspects of using older designs are lost.  However, with Micron’s support documents and a fast-growing ecosystem, you’ll be up-to-speed in no time.

What are the measurable benefits of HMC?

HMC is a revolutionary innovation in DRAM memory architecture that delivers memory performance, power, reliability, and cost like never before. This major technology leap breaks through the memory wall, unlocking previously unthinkable processing power and ushering in a new generation of computing.

  • Increased Bandwidth − A single HMC unit can provide up to 15 times the bandwidth of a DDR3-1333 module.
  • Reduced Latency – With vastly more responders built into HMC, we expect lower queue delays and higher bank availability, which will provide a substantial system latency reduction—a key advantage in networking system design.
  • Power Efficiency − HMC’s revolutionary architecture enables greater power efficiency and energy savings, utilizing up to 70% less energy per bit than DDR3-1333 DRAM technologies.
  • Smaller Physical Footprint − HMC’s stacked architecture uses nearly 90% less physical space than today’s RDIMMs.
  • Pliable to Multiple Platforms − Logic layer flexibility enables HMC to be tailored to multiple platforms and applications.
  • Ultra Reliability HMC delivers greater resilience and field reparability with a new paradigm of system-level, advanced reliability, availability, and serviceability (RAS) features that include embedded error-checking and correction capabilities.
  • Abstracted Memory − Designers can leverage HMC’s revolutionary features and performance without having to interface with complex memory parameters. HMC manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation.
What does the HMCC specification cover?

The specification includes two PHY definitions and a common protocol. The short-reach (SR) PHY is designed for applications needing channel lengths up to 8 inches, and the ultra short-reach (USR) PHY is intended for applications requiring very short and power-efficient channels with lengths from 1 to 2 inches.

When is Micron planning for HMC volume production?

2014.

Products and Support FAQs (1)

Who do I contact if I have questions about my buymicron.com order?
If you have any questions about your order, contact buymicron.com.

Accelerating System Bandwidth with Serial Memory Solutions Using Hybrid Memory Cube Technology

January 29, 2014 by

For over 4 years, Micron and Altera have been collaborating on HMC technologies. This ongoing work led to the industry’s first demonstration of a working HMC controller, announced last September and demonstrated at the Supercomputing ’13 Conference in Denver. The working demonstration board consists of one Micron® HMC short reach (SR) device and four 28nm Altera Stratix V FPGAs, each of which has 40 GB/s of bandwidth for 160 GB/s of total bandwidth. This demonstration of Strati...Read More

See all posts on HMC, Performance

Latest Blog Posts

Micron's Chief Technologist Featured in EDN's Profiles in Design Series

January 28, 2014 by

Last week, our very own Tom Pawlowski was featured in EDN's Profiles in Design series leading up to his keynote address at this year's DesignCon. If you're planning to attend DesignCon at the Santa Cl...Read More


Automata Processor: It’s Not Just About Speed and Power Consumption

December 19, 2013 by Paul Dlugosch

At Supercomputing 13 (SC13), I participated in a discussion panel on the topic of reconfigurable computing.  One recurring theme expressed by the audience was disappointment that the industry is ...Read More