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Memory for Automotive

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About Micron

Where there's memory, there's Micron

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For more than 30 years Micron has redefined innovation by designing, developing, and manufacturing some of the world’s most advanced technologies.

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Elpida is Now Micron

Elpida Is Now Micron

With the combined strength of our products, technology, and team members—our customers now have access to the broadest portfolio of best-in-class technology.

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A Revolution in Memory

Intel's Xeon PhiTM Performance Unleashed by Micron's On-Package Memory

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Multi-core processing is bringing incredible advances to supercomputing and advanced networking systems— advances that require a new level of memory efficiency and performance. In October, 2011, we joined a group of industry leaders to develop an entirely new memory architecture—the Hybrid Memory Cube (HMC)—which maximizes the full potential of these high-performance systems. HMC represents a fundamental change in how memory is used in the system. This elemental change is paramount. By tightly coupling intelligent memory with CPUs, GPUs, and ASICs, systems can enable dramatic improvements in efficiency and power optimization.

Hybrid Memory Cube

How HMC Works

At the core of the HMC is a small, high-speed logic layer that sits below vertical stacks of DRAM die that are connected using through-silicon-via (TSV) interconnects. The DRAM has been designed solely to handle data, with the logic layer handling all DRAM control within the HMC. System designers have the option of using the HMC as either "near memory," mounted directly adjacent to the processors for best performance, or in a scalable module form factor as "far memory," for optimized power efficiency.

HMC Consortium

The HMC Consortium (HMCC) is a working group made up of industry leaders who build, design in, or enable HMC technology. The HMCC is led by eight developers—Altera, ARM, IBM, SK Hynix, Micron, Open-Silicon, Samsung, and Xilinx—and drives broad agreement of HMC standards with the help of more than 120 consortium adopters. The HMC 1.0 Specification was finalized and released to the public on April 2, 2013 and includes two PHY definitions: the short-reach (SR) designed for applications needing channel lengths up to 8 inches and the ultra short-reach (USR) for applications requiring very short and power-efficient channels with lengths from 1 to 2 inches. The SR PHY targets the networking segment that provides high-bandwidth memory buffering capacity while the USR PHY provides optimum efficiency for the high-performance computing segment.

Today, the HMCC continues to drive industry adoption of this revolutionary memory with the development of a second generation specification designed to increase both short-reach and ultra short-reach performance. This next specification is targeted for completion and release by mid-2014.

  • Micron & Altera's HMC/Stratix V Interoperability Team
    Named 2014 Design Team of the Year by EE Times and EDN
  • Hybrid Memory Cube Named 2013 Product of the Year

Award-Winning Technology

HMC has been recognized by industry leaders and influencers as the long-awaited answer to the growing gap between the performance improvement rate of DRAM versus processor data consumption rate—a dilemma known as the “memory wall.”

Want to Know More?

Learn more about our Short-Reach HMC, including benefits and FAQs, that are available to take your design to the next level.

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Supercomputing Memory

Supercomputing Memory

We offer best-in-class solutions that deliver power efficiency, performance, and reliability for critical workloads.

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