A New Blueprint for Memory Architecture
We are pleased to announce that the HMC specification has now been finalized and published!
For more information, visit the HMCC web site
The Hybrid Memory Cube (HMC) represents a fundamental change in how memory is used in the system. This elemental change is paramount—by tightly coupling intelligent memory with CPUs, GPUs, and ASICs, systems can enable dramatic improvements in efficiency and power optimization.
At the core of the HMC is a small, high-speed logic layer that sits below vertical stacks of DRAM die that are connected using through-silicon-via (TSV) interconnects. The DRAM has been designed solely to handle data, with the logic layer handling all DRAM control within the HMC. System designers have the option of using the HMC as either "near memory," mounted directly adjacent to the processors for best performance, or in a scalable module form factor as "far memory," for optimized power efficiency.
Unprecedented System Performance
- Reduced latency – With vastly more responders built into HMC, we expect lower queue delays and higher bank availability, which can provide a substantial system latency reduction, which is especially attractive in network system architectures.
- Increased bandwidth — A single HMC can provide more than 15X the performance of a DDR3 module. Speed is increased by the very fast, innovative interface, unlike the slower parallel interface used in current DRAM modules.
- Power reductions — HMC is exponentially more efficient than current memory, using 70% less energy per bit than DDR3.
- Smaller physical systems — HMC’s stacked architecture uses nearly 90% less space than today’s RDIMMs.
- Pliable to multiple platforms — Logic-layer flexibility allows HMC to be tailored to multiple platforms and applications.
About the HMC Consortium
The HMC Consortium (HMCC) is a working group made up of industry leaders that might build, design in, or enable HMC technology. The group—which includes Micron Technology, Inc., Samsung Electronics Co., Ltd., Altera Corporation, IBM Corporation, Open-Silicon, Inc., Xilinx, Inc., ARM Ltd., and SK Hynix, Inc.—worked for 17 months to define the HMC interface specification to maximize the capabilities of the next generation of memory-based solutions. Over 100 additional organizations joined the consortium as adopters, providing input and performing reviews during the specification development process.
Visit the HMC Consortium Web site.
Want to Know More?
For more information about Micron's Hybrid Memory Cube technology, see our HMC video on the Innovations page. To request a data sheet, please contact us.