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Data sheet Uploaded 12/2013

Command and Address Setup, Hold, and Derating

Command and Address Setup, Hold, and Derating

The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Command and Address Setup and Hold Values Referenced – AC/DC-Based ; values come from Electrical Characteristics and AC Operating Conditions ) to the ΔtIS and ΔtIH derating values (see Derating Values for tIS/tIH – AC175/DC100-Based and Derating Values for tIS/tIH – AC150/DC100-Based ), respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Derating Values for tIS/tIH – AC150/DC100-Based ).

Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC) (see Input Signal for input signal requirements). For slew rates that fall between the values listed in Derating Values for tIS/tIH – AC150/DC100-Based and Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition , the derating values may be obtained by linear interpolation.

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derating value (see Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ). If the actual signal is later than the nominal slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Tangent Line for tIS (Command and Address – Clock) ).

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Nominal Slew Rate for tIH (Command and Address – Clock) ). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for derating value (see Tangent Line for tIH (Command and Address – Clock) ).

Table 1. Command and Address Setup and Hold Values Referenced – AC/DC-Based
Symbol 800 1066 1333 1600 1866 2133 Unit Reference
tIS(base, AC175) 200 125 65 45 ps VIH(AC)/VIL(AC)
tIS(base, AC150) 350 275 190 170 ps VIH(AC)/VIL(AC)
tIS(base, AC135) 65 60 ps VIH(AC)/VIL(AC)
tIS(base, AC125) 150 135 ps VIH(AC)/VIL(AC)
tIH(base, DC100) 275 200 140 120 100 95 ps VIH(DC)/VIL(DC)
Table 2. Derating Values for tIS/tIH – AC175/DC100-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
AC175 Threshold: VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CMD/ADDR Slew Rate V/ns CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100
1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 –2 –4 –2 –4 –2 –4 6 4 14 12 22 20 30 30 38 46
0.8 –6 –10 –6 –10 –6 –10 2 –2 10 6 18 14 26 24 34 40
0.7 –11 –16 –11 –16 –11 –16 –3 –8 5 0 13 8 21 18 29 34
0.6 –17 –26 –17 –26 –17 –26 –9 –18 –1 –10 7 –2 15 8 23 24
0.5 –35 –40 –35 –40 –35 –40 –27 –32 –19 –24 –11 –16 –2 –6 5 10
0.4 –62 –60 –62 –60 –62 –60 –54 –52 –46 –44 –38 –36 –30 –26 –22 –10
Table 3. Derating Values for tIS/tIH – AC150/DC100-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
AC150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CMD/ADDR Slew Rate V/ns CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100
1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 0 –4 0 –4 0 –4 8 4 16 12 24 20 32 30 40 46
0.8 0 –10 0 –10 0 –10 8 –2 16 6 24 14 32 24 40 40
0.7 0 –16 0 –16 0 –16 8 –8 16 0 24 8 32 18 40 34
0.6 –1 –26 –1 –26 –1 –26 7 –18 15 –10 23 –2 31 8 39 24
0.5 –10 –40 –10 –40 –10 –40 –2 –32 6 –24 14 –16 22 –6 30 10
0.4 –25 –60 –25 –60 –25 –60 –17 –52 –9 –44 –1 –36 7 –26 15 –10
Table 4. Derating Values for tIS/tIH – AC135/DC100-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
AC135 Threshold: VIH(AC) = VREF(DC) + 135mV, VIL(AC) = VREF(DC) - 135mV
CMD/ADDR Slew Rate V/ns CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100
1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 2 –4 2 –4 2 –4 10 4 18 12 26 20 34 30 42 46
0.8 3 –10 3 –10 3 –10 11 –2 19 6 27 14 35 24 43 40
0.7 6 –16 6 –16 6 –16 14 –8 22 0 30 8 38 18 46 34
0.6 9 –26 9 –26 9 –26 17 –18 25 –10 33 –2 41 8 49 24
0.5 5 –40 5 –40 5 –40 13 –32 21 –24 29 –16 37 –6 45 10
0.4 –3 –60 –3 –60 –3 –60 6 –52 14 –44 22 –36 30 –26 38 –10
Table 5. Derating Values for tIS/tIH – AC125/DC100-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
AC125 Threshold: VIH(AC) = VREF(DC) + 125mV, VIL(AC) = VREF(DC) - 125mV
CMD/ADDR Slew Rate V/ns CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100
1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 4 –4 4 –4 4 –4 12 4 20 12 28 20 36 30 44 46
0.8 6 –10 6 –10 6 –10 14 –2 22 6 30 14 38 24 45 40
0.7 11 –16 11 –16 11 –16 19 –8 27 0 35 8 43 18 51 34
0.6 16 –26 16 –26 16 –26 24 –18 32 –10 40 –2 48 8 56 24
0.5 15 –40 15 –40 15 –40 23 –32 31 –24 39 –16 47 –6 55 10
0.4 13 –60 13 –60 13 –60 21 –52 29 –44 37 –36 45 –26 53 –10
Table 6. Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition

Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) tVAC at 135mV (ps) tVAC at 125mV (ps)
>2.0 75 175 168 173
2.0 57 170 168 173
1.5 50 167 145 152
1.0 38 130 100 110
0.9 34 113 85 96
0.8 29 93 66 79
0.7 22 66 42 56
0.6 Note 1 30 10 27
0.5 Note 1 Note 1 Note 1 Note 1
<0.5 Note 1 Note 1 Note 1 Note 1

Note

  1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
Figure 1. Nominal Slew Rate and tVAC for tIS (Command and Address – Clock)



Note

  1. The clock and the strobe are drawn on different time scales.

Figure 2. Nominal Slew Rate for tIH (Command and Address – Clock)



Note

  1. The clock and the strobe are drawn on different time scales.

Figure 3. Tangent Line for tIS (Command and Address – Clock)



Note

  1. The clock and the strobe are drawn on different time scales.

Figure 4. Tangent Line for tIH (Command and Address – Clock)



Note

  1. The clock and the strobe are drawn on different time scales.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Data Setup, Hold, and Derating

Data Setup, Hold, and Derating

The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ; values come from Electrical Characteristics and AC Operating Conditions ) to the ΔtDS and ΔtDH derating values (see Derating Values for tDS/tDH – AC175/DC100-Based ), respectively. Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ).

Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC)) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH/VIL(AC). For slew rates that fall between the values listed in Derating Values for tDS/tDH – AC150/DC100-Based , the derating values may obtained by linear interpolation.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derating value (see Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ). If the actual signal is later than the nominal slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Tangent Line for tDS (DQ – Strobe) ).

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Nominal Slew Rate for tDH (DQ – Strobe) ). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating value (see Tangent Line for tDH (DQ – Strobe) ).

Table 1. DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
Symbol 800 1066 1333 1600 1866 2133 Unit Reference
tDS (base) AC175 75 25 ps VIH(AC)/VIL(AC)
tDS (base) AC150 125 75 30 10 ps VIH(AC)/VIL(AC)
tDS (base) AC135 165 115 60 40 68 53 ps VIH(AC)/VIL(AC)
tDH (base) DC100 150 100 65 45 70 55 ps VIH(DC)/VIL(DC)
Slew Rate Referenced 1 1 1 1 2 2 V/ns
Table 2. Derating Values for tDS/tDH – AC175/DC100-Based

Shaded cells indicate slew rate combinations not supported

ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 88 50 88 50 88 50                    
1.5 59 34 59 34 59 34 67 42                
1.0 0 0 0 0 0 0 8 8 16 16            
0.9     –2 –4 –2 –4 6 4 14 12 22 20        
0.8         –6 –10 2 –2 10 6 18 14 26 24    
0.7             –3 –8 5 0 13 8 21 18 29 34
0.6                 –1 –10 7 –2 15 8 23 24
0.5                     –11 –16 –2 –6 5 10
0.4                         –30 –26 –22 –10
Table 3. Derating Values for tDS/tDH – AC150/DC100-Based

Shaded cells indicate slew rate combinations not supported

ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 75 50 75 50 75 50                    
1.5 50 34 50 34 50 34 58 42                
1.0 0 0 0 0 0 0 8 8 16 16            
0.9     0 –4 0 –4 8 4 16 12 24 20        
0.8         0 –10 8 –2 16 6 24 14 32 24    
0.7             8 –8 16 0 24 8 32 18 40 34
0.6                 15 –10 23 –2 31 8 39 24
0.5                     14 –16 22 –6 30 10
0.4                         7 –26 15 –10
Table 4. Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns

Shaded cells indicate slew rate combinations not supported

ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 68 50 68 50 68 50
1.5 45 34 45 34 45 34 53 42
1.0 0 0 0 0 0 0 8 8 16 16
0.9 2 –4 2 –4 10 4 18 12 26 20
0.8 3 –10 11 –2 19 6 27 14 35 24
0.7 14 –8 22 0 30 8 38 18 46 34
0.6 25 –19 33 –2 41 8 49 24
0.5 29 –16 37 –6 45 –10
0.4 30 26 38 –10
Table 5. Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns

Shaded cells indicate slew rate combinations not supported

ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate
8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
4.0 34 25 34 25 34 25
3.5 29 21 29 21 29 21 29 21
3.0 23 17 23 17 23 17 23 17 23 17
2.5 14 10 14 10 14 10 14 10 14 10
2.0 0 0 0 0 0 0 0 0 0 0
1.5 –23 –17 –23 –17 –23 –17 –23 –17 –15 –19
1.0 –68 –50 –68 –50 –68 –50 –60 –42 –52 –34
0.9 –66 –54 –66 –54 –58 –46 –50 –38 –42 –30
0.8 –64 60 –56 –52 –48 –40 –40 –36 –32 –26
0.7 –53 –59 –45 –51 –37 –43 –29 –33 –21 –17
0.6 –43 –61 –35 –53 –27 –43 –19 –27
0.5 –39 –66 –31 –56 –23 –40
0.4 –38 –76 –30 –60
Table 6. Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition

Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) tVAC at 135mV (ps)
DDR3-800/1066 DDR3-800/1066/1333/1600 DDR3-800/1066/1333/1600 DDR3-1866 DDR3-2133
>2.0 75 105 113 93 73
2.0 57 105 113 93 73
1.5 50 80 90 70 50
1.0 38 30 45 25 5
0.9 34 13 30 Note 1 Note 1
0.8 29 Note 1 11 Note 1 Note 1
0.7 Note 1 Note 1 Note 1 Note 1 Note 1
0.6 Note 1 Note 1 Note 1 Note 1 Note 1
0.5 Note 1 Note 1 Note 1 Note 1 Note 1
<0.5 Note 1 Note 1 Note 1 Note 1 Note 1

Note

  1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
Figure 1. Nominal Slew Rate and tVAC for tDS (DQ – Strobe)



Note

  1. The clock and the strobe are drawn on different time scales.

Figure 2. Nominal Slew Rate for tDH (DQ – Strobe)



Note

  1. The clock and the strobe are drawn on different time scales.

Figure 3. Tangent Line for tDS (DQ – Strobe)



Note

  1. The clock and the strobe are drawn on different time scales.

Figure 4. Tangent Line for tDH (DQ – Strobe)



Note

  1. The clock and the strobe are drawn on different time scales.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

Commands – Truth Tables

Commands – Truth Tables

Table 1. Truth Table – Command

Notes 1–5 apply to the entire table

Function Symbol CKE CS# RAS# CAS# WE# BA [2:0] An A12 A10 A[11, 9:0] Notes
Prev. Cycle Next Cycle
MODE REGISTER SET MRS H H L L L L BA OP code  
REFRESH REF H H L L L H V V V V V  
Self refresh entry SRE H L L L L H V V V V V 6
Self refresh exit SRX L H H V V V V V V V V 6 , 7
L H H H
Single-bank PRECHARGE PRE H H L L H L BA V V L V  
PRECHARGE all banks PREA H H L L H L V V H V  
Bank ACTIVATE ACT H H L L H H BA Row address (RA)  
WRITE BL8MRS, BC4MRS WR H H L H L L BA RFU V L CA 8
BC4OTF WRS4 H H L H L L BA RFU L L CA 8
BL8OTF WRS8 H H L H L L BA RFU H L CA 8
WRITE
with auto
precharge
BL8MRS, BC4MRS WRAP H H L H L L BA RFU V H CA 8
BC4OTF WRAPS4 H H L H L L BA RFU L H CA 8
BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8
READ BL8MRS, BC4MRS RD H H L H L H BA RFU V L CA 8
BC4OTF RDS4 H H L H L H BA RFU L L CA 8
BL8OTF RDS8 H H L H L H BA RFU H L CA 8
READ
with auto
precharge
BL8MRS, BC4MRS RDAP H H L H L H BA RFU V H CA 8
BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8
BL8OTF RDAPS8 H H L H L H BA RFU H H CA 8
NO OPERATION NOP H H H H H V V V V V 9
Device DESELECTED DES H H H X X X X X X X X 10
Power-down entry PDE H L L H H H V V V V V 6
H V V V
Power-down exit PDX L H L H H H V V V V V 6 , 11
H V V V
ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X 12
ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X  

Notes

  1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-dependent.

  2. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be held HIGH during any normal operation.

  3. The state of ODT does not affect the states described in this table.

  4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers.

  5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”

  6. See Truth Table – CKE for additional information on CKE transition.

  7. Self refresh exit is asynchronous.

  8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0.

  9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing.

  10. The DES and NOP commands perform similarly.

  11. The power-down mode does not perform any REFRESH operations.

  12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initialization) or ZQoper (ZQCL command after initialization).

Table 2. Truth Table – CKE

Notes 1–2 apply to the entire table; see Truth Table – Command for additional command details

Current State3 CKE Command5
(RAS#, CAS#, WE#, CS#)
Action5 Notes
Previous Cycle4
(n - 1)
Present Cycle4
(n)
Power-down L L “Don’t Care” Maintain power-down  
L H DES or NOP Power-down exit  
Self refresh L L “Don’t Care” Maintain self refresh  
L H DES or NOP Self refresh exit  
Bank(s) active H L DES or NOP Active power-down entry  
Reading H L DES or NOP Power-down entry  
Writing H L DES or NOP Power-down entry  
Precharging H L DES or NOP Power-down entry  
Refreshing H L DES or NOP Precharge power-down entry  
All banks idle H L DES or NOP Precharge power-down entry 6
H L REFRESH Self refresh

Notes

  1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

  2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH.

  3. Current state = The state of the DRAM immediately prior to clock edge n.

  4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge.

  5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Truth Table – Command ). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed.

  6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied. All self refresh exit and power-down exit parameters are also satisfied.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.