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MT48LC4M32B2P-6 Part Page Save
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Data Sheets (1)

Orderable Parts (1)» Compare all


 
Orderable Part Information
Status Contact Factory Alternative Part view
FBGA Code N/A SPD Data N/A
MBQual Data N/A Shipping Media N/A
PLP No Start Date N/A


 
Specs
Density 128Mb RoHS Yes
Depth 4Mb Width x32
Voltage 3.3V Package TSOP
Pin Count 86-pin Clock Rate 167 MHz
Cycle Time 6ns Op. Temp. 0C to +70C
CL CL = 3 Data Rate PC133

Recently Added

Date What was added
09/2014 128Mb: x32 SDRAM
02/2007 IBIS

Sim Models & Software

Title & Description Secure ID Updated
IBIS:  2.2 02/2007
HSpice:  2 03/2004
See all Sim Models (4)

Documentation & Support

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For MT48LC4M32B2P-6 (3)
Title & Description Secure ID# Updated Type
AddEmailRoHS Certificate of Compliance: (PDF 244 KB) Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive. 10/2014 RoHS Certification
AddChina RoHS Certificate: (PDF 244 KB) Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products. 10/2014 RoHS Certification
128Mb: x32 SDRAM: (PDF 3.52 MB) 09/2014 Data Sheet
For SDRAM (9)
Title & Description Secure ID# Updated Type
Industrial and Multimarket Application Memory Flyer: (PDF 398.61 KB) Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multimarket segments. 09/2014 Product Flyer
SDRAM I/O Characteristics Comparison of 54nm to 130nm Die: (PDF 515.31 KB)This technical note compares the I/O characteristics of the 54nm to the 130nm single data rate (SDR) synchronous dynamic random access memory (SDRAM) die. TN-00-24 08/2011 Technical Note
LVTTL Derating for SDRAM Slew Rate Violations: (PDF 318.64 KB) Describes the proper setup and hold time derating when the slew rate during transition time violates specification. TN-48-09 11/2009 Technical Note
SDRAM System-Power Calculator: (XLS 54 KB) 11/2009 Power Calculator
Designing Competitive DDR Platforms: (PDF 2.64 MB) 11/2009 Presentation
Thinning Considerations for Wafer Products: (PDF 73.58 KB)Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 Technical Note
Backward Compatibility for Faster SDRAM: (PDF 79.21 KB)Reviews the timing differences between SDRAM generations and shows how the faster Micron parts are compatible with the slower parts TN-48-15 10/2005 Technical Note
Designing in SDRAM for Future Upgrades: (PDF 126.15 KB)Describes how to design in SDRAM for future upgrades TN-48-08 03/2004 Technical Note
Interfacing SDRAM Devices with Motorola's MPC8xx: (PDF 176.99 KB)Describes how to interface SDRAM devices with Motorola's MPC8xx TN-48-12 12/2001 Technical Note
For DRAM (16)
Title & Description Secure ID# Updated Type
HMC Part Numbering System: (PDF 59 KB)Part numbering guide for Hybrid Memory Cube 10/2014 Part Numbering Guide
DRAM Component Part Numbering System: (PDF 46.77 KB)Part numbering guide for DDR4/DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 10/2014 Part Numbering Guide
Legacy LPDRAM Part Numbering System: (PDF 114.47 KB)Part numbering guide for legacy LPDDR2 and LPDRR3 PoP and FBGA components 05/2014 Part Numbering Guide
SEMI Wafer Map Format: (PDF 114.26 KB)Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 03/2014 Technical Note
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
Recommended Soldering Parameters: (PDF 173.37 KB)Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 12/2012 Technical Note
Bypass Capacitor Selection for High-Speed Designs: (PDF 481.9 KB)Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 Technical Note
Micron Wire-Bonding Techniques: (PDF 66.13 KB)This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 Technical Note
Uprating of Semiconductors for High-Temperature Applications: (PDF 428.33 KB)Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 Technical Note
Accelerate Design Cycles with Simulation Models: (PDF 206.91 KB)Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 Technical Note
The Future of Memory and Storage: (PDF 1.54 MB)Overview of trends for main memory and Flash memory 12/2009 Presentation
Understanding Signal Integrity: (PDF 1.64 MB)Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 Technical Note
IBIS Behavioral Models: (PDF 163.98 KB)Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 Technical Note
Understanding Quality and Reliability Requirements for Bare Die Applications: (PDF 142.04 KB)Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 Technical Note
FBGA Date Codes: (PDF 22.36 KB)Date codes for FBGA-packaged components 08/2005 Part Numbering Guide
FBGA Decoder: Micron's FBGA Part Marking Decoder makes it easier to understand part marking. Tool
For Products and Support (14)
Title & Description Secure ID# Updated Type
Product Marks/Product and Packaging Labels: (PDF 1.58 MB)Explains product part marking, and product and packaging labels. CSN-11 10/2014 Customer Service Note
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron Component and Module Packaging: (PDF 1.41 MB)Explanation of Micron packaging labels and procedures. CSN-16 01/2013 Customer Service Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.

For MT48LC4M32B2P-6 (4)
Title & Description Secure ID# Updated Type
IBIS: (ZIP 27.45 KB)2.2 02/2007 Sim Model
IBIS: (ZIP 28.13 KB)2.3 02/2007 Sim Model
HSpice: (ZIP 88.25 KB)2 03/2004 Sim Model
Verilog: (ZIP 8.99 KB) 09/2000 Sim Model
For SDRAM (0)
Title & Description Secure ID# Updated Type
For DRAM (0)
Title & Description Secure ID# Updated Type
For Products and Support (0)
Title & Description Secure ID# Updated Type

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.

Disclaimers

  1. Micron Models: By downloading any Micron model from this site, you must agree to the terms of Micron's Simulation Models License Agreement. If you do not agree to terms, you do not have permission to use the site or download material from it.
  2. Non-Micron Models: For your convenience, Micron links to third-party simulation models. Note that Micron does not guarantee functionality or accuracy of these models.

SDRAM FAQs (3)

Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.

DRAM FAQs (8)

What is a "bank"?
A bank is an array of memory bits. Multiple arrays or banks are contained within a DRAM component. Depending on density, DRAM components may consist of 4 or 8 banks. For example, a bank may consist of 32 million rows, 4 bits across. This would equate to 128 megabits. Four of these banks in a single DRAM component would yield a 512Mb component.
What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect reference resistor connected to ZQ pin?
The impedance tolerance of the driver is ±15 percent.
Does thermal information change for IT parts?
Thermal information includes temperature limits and thermal impedance values. Temperature limits do change for IT parts (TC, TJ, and TA), but thermal impedance values (θJA, θJB, and θJC) do not because thermal impedance depends primarily on the package.
My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t swing past that on transitions.
Your particular board design should not be a cause of major concern. The pins can handle the VDD voltage regardless of the VDDQ voltage.
Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point application?
The ECC chip(s) should share the same CKE and CS# as the other devices because they are accessed as the same piece of data.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.

Products and Support FAQs (1)

Who do I contact if I have questions about my buymicron.com order?
If you have any questions about your order, contact buymicron.com.