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MT41J128M16HA-15E IT Part Page Save
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Data Sheets (1)

Orderable Parts (1)» Compare all

Orderable Part Information
Status Contact Factory Alternative Part view
MBQual Data N/A Shipping Media N/A
PLP No Start Date N/A

Density 2Gb RoHS Yes
Depth 128Mb Width x16
Voltage 1.5V Package FBGA
Pin Count 96-ball Clock Rate 667 MHz
Cycle Time 1.5ns Op. Temp. -40C to +95C
CL CL = 9 Data Rate DDR3-1333

Recently Added

Date What was added
10/2014 2Gb: x4, x8, x16 DDR3 SDRAM
04/2014 DDR3 SDRAM Verilog Model

Sim Models & Software

Title & Description Secure ID Updated
DDR3 SDRAM Verilog Model:  1.70 04/2014
See all Sim Models (1)

Documentation & Support



For MT41J128M16HA-15E IT (3)
Title & Description Secure ID# Updated Type
AddEmailRoHS Certificate of Compliance: (PDF 244 KB) Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive. 11/2014 RoHS Certification
AddChina RoHS Certificate: (PDF 244 KB) Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products. 11/2014 RoHS Certification
2Gb: x4, x8, x16 DDR3 SDRAM: (PDF 3.21 MB) 10/2014 Data Sheet
For DDR3 SDRAM (25)
Title & Description Secure ID# Updated Type
Industrial and Multimarket Application Memory Flyer: (PDF 398.61 KB) Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multimarket segments. 09/2014 Product Flyer
User's Manual: New Features of DDR3 SDRAM: (PDF 169.49 KB)This manual is intended for users who design application systems using DDR3 SDRAM manufactured by Elpida. E1503E10 02/2014 Technical Note
Technical Note: Recommended Soldering Conditions & Storage Conditions: (PDF 194.25 KB)This document shows referential examples of recommended soldering and storage conditions for DRAM products provided by Elpida Memory, Inc. E0591E22 02/2014 Technical Note
Technical Note: DDR3 8Gb DDP 2CS to 8Gb SDP 1CS Transition Guide: (PDF 197.77 KB)This technical note explains how to transition a dual-rank 8Gb 2CS (dual die) MT41K512M16 DDP device to a single-rank 8Gb 1CS (monolithic) MT41K512M16 SDP device. TN-41-16 02/2014 Technical Note
DDR3 Point-to-Point Design Support: (PDF 660.41 KB)DDR3 is an evolutionary transition from DDR2. TN-41-13 08/2013 Technical Note
DDR3 SDRAM VOL and VOH Specifications: (PDF 240.17 KB)Describes proper interpretation and use of VOL and VOH specifications. TN-41-15 07/2013 Technical Note
Networking Solutions Guide: (PDF 240.27 KB)This guide outlines Micron’s various solutions—from DRAM components and modules to NOR and NAND Flash to solid state drives (SSDs)—available for networking applications. 06/2013 Product Flyer
A Micron/Engicam Case Study: When Versatility and Durability Matter Most: (PDF 1.29 MB) 02/2013 Case Study
Why DRAM for Ultrathins: (PDF 64.92 KB)Micron’s DRAM portfolio is the industry’s broadest and includes every type and form factor used in today’s ultrathin and Ultrabook designs. 02/2013 Product Flyer
Error Correction Code in SoC FPGA-Based Memory Systems: (PDF 361.92 KB)This presentation will examine the potential sources and implications of soft errors and explain an error detection and correction method implemented by Altera and Micron to make embedded systems more resilient to these types of soft errors. 04/2012 White Paper
DDR3L SDRAM System-Power Calculator: (XLSM 197.81 KB) 07/2011 Power Calculator
DDR3 SDRAM System-Power Calculator: (XLSM 195.3 KB)Version 0.9 12/2010 Power Calculator
DDR3 Thermals: (PDF 1.32 MB)Thermal limits, operating temperatures, tools, and system development 12/2009 Presentation
DDR3 - What's New: (PDF 404.43 KB)Technology trends, market forecast, road maps 12/2009 Presentation
Server Memory Solutions for the Impending Data Center Power Crisis: (PDF 309.03 KB)Facts about data center energy consumption and information about how to achieve significant power savings with Micron's low-voltage memory modules for servers. 12/2009 White Paper
DDR3 RDIMMs Channel: (PDF 1.15 MB)Basics, topology, simulations, and timing 12/2009 Presentation
DDR3 Power: (PDF 598.62 KB)Estimates, effects of bandwidth, and comparisons to DDR2 12/2009 Presentation
DDR3 Advantages Presentation: (PDF 365.19 KB)Covers power, speed, performance, and more 12/2009 Presentation
Thinning Considerations for Wafer Products: (PDF 73.58 KB)Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 Technical Note
DDR3 Power-Up, Initialization, and Reset: (PDF 504.77 KB)Describes power-up, initialization, and reset with DDR3. TN-41-07 10/2008 Technical Note
Design Guide - Dealing with DDR2/DDR3 Clock Jitter: (PDF 272.53 KB)Explores DDR2/DDR3 clock jitter specifications and provides guidance on how to apply them and how to deal with violations TN-04-56 09/2008 Technical Note
DDR3 Termination Data Strobe : (PDF 152.41 KB)Provides guidelines for using the TDQS feature to reduce signal integrity issues associated with mismatched DQS loading in in combined x4-based/x8-based systems TN-41-06 03/2008 Technical Note
DDR3 Dynamic On-Die Termination : (PDF 370.26 KB)With DDR3, dynamic ODT provides systems with increased flexibility to optimize termination values for different loading conditions TN-41-04 03/2008 Technical Note
DDR3 ZQ Calibration: (PDF 250.61 KB)Describes how the DDR3 SDRAM driver design has been enhanced TN-41-02 02/2008 Technical Note
Calculating Memory System Power For DDR3 : (PDF 1.12 MB)Details how DDR3 SDRAM consumes power and provides the tools that system designers can use to estimate power consumption. TN-41-01 05/2007 Technical Note
For DRAM (15)
Title & Description Secure ID# Updated Type
HMC Part Numbering System: (PDF 59 KB)Part numbering guide for Hybrid Memory Cube 10/2014 Part Numbering Guide
DRAM Component Part Numbering System: (PDF 46.77 KB)Part numbering guide for DDR4/DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 10/2014 Part Numbering Guide
Legacy LPDRAM Part Numbering System: (PDF 114.47 KB)Part numbering guide for legacy LPDDR2 and LPDRR3 PoP and FBGA components 05/2014 Part Numbering Guide
SEMI Wafer Map Format: (PDF 114.26 KB)Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 03/2014 Technical Note
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
Recommended Soldering Parameters: (PDF 173.37 KB)Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 12/2012 Technical Note
Bypass Capacitor Selection for High-Speed Designs: (PDF 481.9 KB)Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 Technical Note
Micron Wire-Bonding Techniques: (PDF 66.13 KB)This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 Technical Note
Uprating of Semiconductors for High-Temperature Applications: (PDF 428.33 KB)Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 Technical Note
Accelerate Design Cycles with Simulation Models: (PDF 206.91 KB)Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 Technical Note
Understanding Signal Integrity: (PDF 1.64 MB)Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 Technical Note
IBIS Behavioral Models: (PDF 163.98 KB)Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 Technical Note
Understanding Quality and Reliability Requirements for Bare Die Applications: (PDF 142.04 KB)Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 Technical Note
FBGA Date Codes: (PDF 22.36 KB)Date codes for FBGA-packaged components 08/2005 Part Numbering Guide
FBGA Decoder: Micron's FBGA Part Marking Decoder makes it easier to understand part marking. Tool
For Products and Support (14)
Title & Description Secure ID# Updated Type
Micron Component and Module Packaging: (PDF 1.35 MB)Explanation of Micron packaging labels and procedures. CSN-16 11/2014 Customer Service Note
Product Marks/Product and Packaging Labels: (PDF 1.58 MB)Explains product part marking, and product and packaging labels. CSN-11 10/2014 Customer Service Note
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.

For MT41J128M16HA-15E IT (1)
Title & Description Secure ID# Updated Type
DDR3 SDRAM Verilog Model: (ZIP 59.56 KB)1.70 04/2014 Sim Model
For DDR3 SDRAM (0)
Title & Description Secure ID# Updated Type
For DRAM (0)
Title & Description Secure ID# Updated Type
For Products and Support (0)
Title & Description Secure ID# Updated Type

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.


  1. Micron Models: By downloading any Micron model from this site, you must agree to the terms of Micron's Simulation Models License Agreement. If you do not agree to terms, you do not have permission to use the site or download material from it.
  2. Non-Micron Models: For your convenience, Micron links to third-party simulation models. Note that Micron does not guarantee functionality or accuracy of these models.


What is the RESET# pin used for?
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs and ODT will tri-state. The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
What is the output driver impedance for DDR3?
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
What is the operating voltage?
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V.
What is "write leveling"?
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
Are the DDR3 voltages backward compatible?

Yes, all of our 1.35V parts are backward compatible with 1.5V.

Will Micron support an extended temperature range for DDR3?
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.
What is "ZQ Calibration"?
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
What is the "MPR"?
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
How do I determine the amount of time between ZQCS commands?
Each ZQCS command can correct a minimum of 0.5 percent impedance error within 64 clocks. To calculate the ZQCS interval, use the following formula: ZQCS Interval =ZQCorrection (Tsens x Tdriftrate) + (VSens x Vdriftrate) For the sensitivities, use the MAX number from the ODT voltage and temperature sensitivity table in the component specification. Drift rates will vary from system to system. ZQCorrection equals 0.5%/64 clocks.
How do I determine my CAS WRITE latency (CWL)?
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
Can I run Micron’s DDR3 memory at clock speeds slower than 300 MHz?
Yes. Micron supports the optional feature to disable the DLL. This feature allows the DRAM to operate at frequencies slower than 125 MHz. A minimum clock rate is not specified, but the timing still must satisfy the refresh interval (tREFI). When operating in DLL disable mode, special conditions apply: - no support of on-die termination (ODT); ODT must be disabled or turned off - both CL and CWL must be equal to 6 - data out is no longer edge-aligned to the clock and read latency will be AL + CL - 1 tCK
What component densities are available?
JEDEC has defined DDR3 densities of 512Mb–8Gb; Micron plans to support 1Gb through 4Gb.
What is the difference between the ZQCL and ZQCS commands?
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
What is Dynamic ODT?
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
What is burst chop?
Due to DDR3's use of the 8n-prefetch architecture, a true burst of 4 is not possible with most designs. Burst chop mode (BC4) is unique to DDR3. In this mode, the last 4 bits of the burst are essentially masked. Timing in BC4 cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized.


What is a "bank"?
A bank is an array of memory bits. Multiple arrays or banks are contained within a DRAM component. Depending on density, DRAM components may consist of 4 or 8 banks. For example, a bank may consist of 32 million rows, 4 bits across. This would equate to 128 megabits. Four of these banks in a single DRAM component would yield a 512Mb component.
What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect reference resistor connected to ZQ pin?
The impedance tolerance of the driver is ±15 percent.
Does thermal information change for IT parts?
Thermal information includes temperature limits and thermal impedance values. Temperature limits do change for IT parts (TC, TJ, and TA), but thermal impedance values (θJA, θJB, and θJC) do not because thermal impedance depends primarily on the package.
My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t swing past that on transitions.
Your particular board design should not be a cause of major concern. The pins can handle the VDD voltage regardless of the VDDQ voltage.
Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point application?
The ECC chip(s) should share the same CKE and CS# as the other devices because they are accessed as the same piece of data.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.

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