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MT47H32M16HR-25E Part Page Save
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Data Sheets (1)

Orderable Parts (1)» Compare all

Orderable Part Information
Status Contact Factory Alternative Part view
MBQual Data N/A Shipping Media N/A
PLP No Start Date N/A

Density 512Mb RoHS Yes
Depth 32Mb Width x16
Voltage 1.8V Package FBGA
Pin Count 84-ball Clock Rate 400 MHz
Cycle Time 2.5ns Op. Temp. 0C to +85C
CL CL = 5 Data Rate DDR2-800

Recently Added

Date What was added
04/2014 512Mb: x4, x8, x16 DDR2 SDRAM
04/2013 IBIS

Sim Models & Software

Title & Description Secure ID Updated
512Mb DDR2 Verilog Model:  5.83 04/2010
HSpice:  2.0 (Die Rev. G) 08/2010
See all Sim Models (3)

Documentation & Support



For MT47H32M16HR-25E (3)
Title & Description Secure ID# Updated Type
AddEmailRoHS Certificate of Compliance: (PDF 244 KB) Part-specific certification of how this product meets the requirements of the current DIRECTIVE 2002/95/EC, a.k.a. Restriction of Hazardous Substances (RoHS) Directive. 11/2014 RoHS Certification
AddChina RoHS Certificate: (PDF 244 KB) Part-specific certification as required by China's Management Methods for Controlling Pollution by Electronic Information Products. 11/2014 RoHS Certification
512Mb: x4, x8, x16 DDR2 SDRAM: (PDF 2.08 MB) 04/2014 Data Sheet
For DDR2 SDRAM (26)
Title & Description Secure ID# Updated Type
Industrial and Multimarket Application Memory Flyer: (PDF 398.61 KB) Our extensive and stable portfolio of IMM-focused memory solutions empower technology developments in automotive, industrial, medical, manufacturing, and other multimarket segments. 09/2014 Product Flyer
Technical Note: Recommended Soldering Conditions & Storage Conditions: (PDF 194.25 KB)This document shows referential examples of recommended soldering and storage conditions for DRAM products provided by Elpida Memory, Inc. E0591E22 02/2014 Technical Note
Technical Note: New Function of DDR2 SDRAM - On-Die Termination (ODT): (PDF 211.08 KB)This document describes On-Die Termination (ODT), a new function that has been added to DDR2 SDRAM. E0593E20 02/2014 Technical Note
Technical Note: New Function of DDR2 SDRAM - Off-Chip Driver (OCD): (PDF 146.06 KB)This document describes Off-Chip Driver (OCD), a new function that has been added to DDR2 SDRAM. E0594E20 02/2014 Technical Note
Technical Note: DDR2 SDRAM Technology: (PDF 50.59 KB)This document describes new functions that have been added to DDR2 SDRAM. E0678E10 02/2014 Technical Note
A Micron/Engicam Case Study: When Versatility and Durability Matter Most: (PDF 1.29 MB) 02/2013 Case Study
Error Correction Code in SoC FPGA-Based Memory Systems: (PDF 361.92 KB)This presentation will examine the potential sources and implications of soft errors and explain an error detection and correction method implemented by Altera and Micron to make embedded systems more resilient to these types of soft errors. 04/2012 White Paper
DDR2 (Point-to-Point) Features and Functionality: (PDF 706.41 KB)Rev B. Focuses on the unique memory requirements of point-to-point design layouts and describes DDR2 features and functionality TN-47-19 03/2011 Technical Note
Calculating Memory System Power for DDR2: (PDF 1.04 MB)Rev. B, Details how DDR2 SDRAM consumes power and provides tools to estimate power consumption in a given system TN-47-04 03/2011 Technical Note
DDR2 tCKE Power-Down Requirement: (PDF 102.03 KB)Describes the tCKE timing parameter of DDR2 SDRAM. TN-47-14 04/2010 Technical Note
Power Solutions for DDR2 Notebook PCs: (PDF 374.42 KB)Technical note providing general guidelines for designing power circuitry for DDR2 memory. Includes the DDR2 voltage requirements and encompasses a sample reference design focused on the Texas Instruments Incorporated (TI) TPS51116 DDR2 memory power solution. TN-47-05 04/2010 Technical Note
DDR2 SDRAM System-Power Calculator: (XLS 139 KB) 01/2010 Power Calculator
DDR2 1.5V Memory: (PDF 548.95 KB)Technical review 12/2009 Presentation
Server Memory Solutions for the Impending Data Center Power Crisis: (PDF 309.03 KB)Facts about data center energy consumption and information about how to achieve significant power savings with Micron's low-voltage memory modules for servers. 12/2009 White Paper
FBDIMM Channel Utilization (Bandwidth and Power): (PDF 1.21 MB)Newly introduced FBDIMMs offer virtually unlimited scalability of density, a significantly reduced number of routed motherboard signals, and high bandwidth solutions, all with an extremely reliable channel protocol TN-47-21 12/2009 Technical Note
Designing for High-Density DDR2 Memory: (PDF 284.38 KB)Focuses on designing for high-density memory—addressing schemes of each density, configurations, and the subtle differences between the 4-bank and new 8-bank DDR2 devices TN-47-16 12/2009 Technical Note
Design Guide for Two-DIMM, Unbuffered Systems: (PDF 614.72 KB)DDR2-533 memory design guide for two-DIMM, unbuffered systems TN-47-01 12/2009 Technical Note
Thinning Considerations for Wafer Products: (PDF 73.58 KB)Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 Technical Note
Design Guide - Dealing with DDR2/DDR3 Clock Jitter: (PDF 272.53 KB)Explores DDR2/DDR3 clock jitter specifications and provides guidance on how to apply them and how to deal with violations TN-04-56 09/2008 Technical Note
Designing for 1.5V, Low-Power FBDIMMs: (PDF 980.89 KB)Discusses memory power trends and identifies new low-voltage solutions for high-density DDR2 memory designs TN-47-22 05/2008 Technical Note
DDR2 (Point-to-Point) Package Sizes and Layout Basics: (PDF 408.8 KB)General guidelines for developing the PCB floor plan TN-47-20 06/2007 Technical Note
DDR2 SDRAM Offers New Features and Functionality: (PDF 400.7 KB)Discusses the various changes in DDR2 technology and the resulting features and benefits TN-47-02 12/2006 Technical Note
DDR2 Package Sizes and Layout Requirements: (PDF 614.31 KB)Covers DDR2 package sizes and layout requirements TN-47-08 11/2005 Technical Note
DDR2 SODIMM Optimized Address/Command Nets: (PDF 592.56 KB)Provides the system-level designer with an overview of the DDR2 SODIMM family and offers insight into termination techniques utilized on the commands and addresses for these modules TN-47-17 05/2005 Technical Note
DDR2 Simulation Support: (PDF 127.84 KB)Covers DDR2 simulation, adding to Micron's extensive array of design support tools for system designers TN-47-07 05/2005 Technical Note
Module Pinout Decoder: (PDF 215.46 KB)Provides sorted pin assignment tables and pin location figures for use in DDR2 DIMM signal identification, tracing, and troubleshooting TN-47-03 12/2004 Technical Note
For DRAM (15)
Title & Description Secure ID# Updated Type
HMC Part Numbering System: (PDF 59 KB)Part numbering guide for Hybrid Memory Cube 10/2014 Part Numbering Guide
DRAM Component Part Numbering System: (PDF 46.77 KB)Part numbering guide for DDR4/DDR3/DDR2/DDR/SDR SDRAM, Mobile LPDRAM, and RLDRAM components 10/2014 Part Numbering Guide
Legacy LPDRAM Part Numbering System: (PDF 114.47 KB)Part numbering guide for legacy LPDDR2 and LPDRR3 PoP and FBGA components 05/2014 Part Numbering Guide
SEMI Wafer Map Format: (PDF 114.26 KB)Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 03/2014 Technical Note
Routing Guidelines for Micron’s HMC-15G-SR: (PDF 3.3 MB)Provides sound methods, proven solutions, and detailed PCB layout guidelines to enable successful designs using Micron’s HMC. TN-43-03 HMC TN-43-03 06/2013 Technical Note
Recommended Soldering Parameters: (PDF 173.37 KB)Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 12/2012 Technical Note
Bypass Capacitor Selection for High-Speed Designs: (PDF 481.9 KB)Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 Technical Note
Micron Wire-Bonding Techniques: (PDF 66.13 KB)This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 Technical Note
Uprating of Semiconductors for High-Temperature Applications: (PDF 428.33 KB)Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 Technical Note
Accelerate Design Cycles with Simulation Models: (PDF 206.91 KB)Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 Technical Note
Understanding Signal Integrity: (PDF 1.64 MB)Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 Technical Note
IBIS Behavioral Models: (PDF 163.98 KB)Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 Technical Note
Understanding Quality and Reliability Requirements for Bare Die Applications: (PDF 142.04 KB)Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 Technical Note
FBGA Date Codes: (PDF 22.36 KB)Date codes for FBGA-packaged components 08/2005 Part Numbering Guide
FBGA Decoder: Micron's FBGA Part Marking Decoder makes it easier to understand part marking. Tool
For Products and Support (14)
Title & Description Secure ID# Updated Type
Micron Component and Module Packaging: (PDF 1.35 MB)Explanation of Micron packaging labels and procedures. CSN-16 11/2014 Customer Service Note
Product Marks/Product and Packaging Labels: (PDF 1.58 MB)Explains product part marking, and product and packaging labels. CSN-11 10/2014 Customer Service Note
Shipping Quantities: (PDF 1.22 MB)Provides standard part quantities for shipping. CSN-04 03/2014 Customer Service Note
RMA Procedures for Packaged Product and Bare Die Devices: (PDF 76.22 KB)Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 01/2014 Customer Service Note
Wafer Packaging and Packaging Materials: (PDF 591.42 KB)Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 11/2013 Customer Service Note
Thermal Applications: (PDF 246.79 KB)Describes some considerations in thermal applications for Micron memory devices TN-00-08 07/2013 Technical Note
Moisture Absorption in Plastic Packages: (PDF 97.08 KB)Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2013 Technical Note
Micron BGA Manufacturer's User Guide: (PDF 388.76 KB)Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 12/2012 Customer Service Note
Electronic Data Interchange: (PDF 52.45 KB)Describes EDI transmission sets, protocol, and contacts. CSN-06 11/2012 Customer Service Note
PCN/EOL Systems: (PDF 79.21 KB)Explains Micron's product change notification and end-of-life systems. CSN-12 04/2012 Customer Service Note
Lead Frame Package User Guidelines: (PDF 245.66 KB)Discusses Micron's lead-frame package options CSN-30 05/2011 Customer Service Note
ESD Precautions for Die/Wafer Handling and Assembly: (PDF 120.81 KB)Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 Customer Service Note
Micron KGD Definitions: (PDF 65.52 KB)Describes the testing specifications and parameters for Micron's KGD-C1 and KGD-C2 DRAM die. CSN-22 07/2009 Customer Service Note
Bare Die SiPs and MCMs: (PDF 151.06 KB)Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 Customer Service Note

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.

For MT47H32M16HR-25E (3)
Title & Description Secure ID# Updated Type
IBIS: (ZIP 6.4 MB)2.1 (Die Rev. G) 04/2013 Sim Model
HSpice: (ZIP 4.17 MB)2.0 (Die Rev. G) 08/2010 Sim Model
512Mb DDR2 Verilog Model: (ZIP 36.49 KB)5.83 04/2010 Sim Model
For DDR2 SDRAM (0)
Title & Description Secure ID# Updated Type
For DRAM (0)
Title & Description Secure ID# Updated Type
For Products and Support (0)
Title & Description Secure ID# Updated Type

Please Note: To view Secure Documents (Secure Lock) please log in or click on a secured document to request access.


  1. Micron Models: By downloading any Micron model from this site, you must agree to the terms of Micron's Simulation Models License Agreement. If you do not agree to terms, you do not have permission to use the site or download material from it.
  2. Non-Micron Models: For your convenience, Micron links to third-party simulation models. Note that Micron does not guarantee functionality or accuracy of these models.


Should the DLL be disabled?
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
Should DDR2 SDRAM always have ODT turned on?
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Is VREF allowed to float during self refresh mode?
No, it must be maintained at VDDQ/2.
What is the DDR2 RDQS pin for?
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
Will the device run at a slow clock (well under the slowest data sheet speed)?
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.
What is the maximum clock rate for DDR2 when it’s used with a single-ended DQS?
The answer depends mostly on design implementation. As long as the data setup and holds have 150ps or more of margin and there’s a fast slew rate, a single-ended DQS should be OK.
What is the difference between 1.5V DDR2 SDRAM and 1.55V DDR2 SDRAM?
1.5V DDR2 SDRAM is not backward compatible to 1.8V operating systems, and the 1.55V DDR2 SDRAM is.
Is the ridge down the middle of the underside of FBGA packages conductive?
No, only designated balls are conductive.
Are there any timing specification differences between 1.5V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Are there any timing specification differences between 1.55V DDR2 SDRAM and 1.8V DDR2 SDRAM?
Yes, DLL-controlled output specs require some derating.
Are there any supply voltage savings with 1.5V DDR2 SDRAM versus 1.55V DDR2 SDRAM?
Yes, the 1.5V DDR2 SDRAM uses about 15–20 percent less current than the 1.55V DDR2 SDRAM.
Can DDR2-1066 be used with two slots?
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
Is DDR2-1066 a JEDEC standard?
Not yet, but it’s in process.
How much power does the Vref power pin draw?
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
Can you explain how on-die termination (ODT) affects power consumption?
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.

In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.


What is a "bank"?
A bank is an array of memory bits. Multiple arrays or banks are contained within a DRAM component. Depending on density, DRAM components may consist of 4 or 8 banks. For example, a bank may consist of 32 million rows, 4 bits across. This would equate to 128 megabits. Four of these banks in a single DRAM component would yield a 512Mb component.
What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect reference resistor connected to ZQ pin?
The impedance tolerance of the driver is ±15 percent.
Does thermal information change for IT parts?
Thermal information includes temperature limits and thermal impedance values. Temperature limits do change for IT parts (TC, TJ, and TA), but thermal impedance values (θJA, θJB, and θJC) do not because thermal impedance depends primarily on the package.
My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t swing past that on transitions.
Your particular board design should not be a cause of major concern. The pins can handle the VDD voltage regardless of the VDDQ voltage.
Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point application?
The ECC chip(s) should share the same CKE and CS# as the other devices because they are accessed as the same piece of data.
Is there a recommended lowest working frequency for SDRAM?
Because SDRAM does not have a DLL, there is no recommended lowest frequency. SDRAM parts will work at very low frequencies if all data sheet specifications are met. It is important to maintain a good slew rate, however, since a very slow slew rate will affect setup and hold-time transitions. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see TN-48-09.
Can the SDRAM clock frequency be changed?
Micron SDRAM data sheets require that the clock frequency be constant during access or precharge states (READ, WRITE, tWR, and PRECHARGE commands). At other times frequency should not matter much because there is no DLL in SDRAM however, we do not recommend it. Lowering SDRAM frequency is OK even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications should be adhered to.
Can CKE be tied HIGH throughout SDRAM operation (initialization and normal operation)?
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.

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