FAQ Category

RLDRAM II FAQs

Recent Questions

• Is MAX power specified in the data sheet?
  
• I’m seeing substantial jitter on my outputs; what can I do to remedy this?
  
• How is RLDRAM II memory similar to SRAM?
  
• Can 2.5V or 3.3V be directly input to joint test action group (JTAG) pins?
  
• Does the RLDRAM internally compensate for voltage and temperature changes when bit A8 is not selected HIGH on the RLDRAM II during setting of the mode register?
  
• How can I reset the RLDRAM II device?
  
• Can I reload the mode register after I have been operating with READs and WRITEs on RLDRAM II memory?
  
• Can RLDRAM II run slower than 175 MHz?
  
• Can I connect the “Do Not Use” (DNU) pins to ground (GND)?
  
• Does the 576Mb RLDRAM II device still support 1.8V VDDQ? Is it possible to run at 533 MHz with VDDQ = 1.8V?
  

More

• What is meant by "In Development," "Advanced," "Sampling," "Production," "Not Recommended," "End of Life," or "Obsolete," part status?
  
• How is RLDRAM II memory similar to SRAM?
  
• Is MAX power specified in the data sheet?
  
• Which high-speed transceiver logic (HSTL) class do the RLDRAM II DQs comply with?
  
• Are CK/CK# and DK/DK# true differential inputs?
  
• Can 2.5V or 3.3V be directly input to joint test action group (JTAG) pins?
  
• Does the RLDRAM internally compensate for voltage and temperature changes when bit A8 is not selected HIGH on the RLDRAM II during setting of the mode register?
  
• I’m seeing substantial jitter on my outputs; what can I do to remedy this?
  
• Can I reload the mode register after I have been operating with READs and WRITEs on RLDRAM II memory?
  
• How can I reset the RLDRAM II device?
  

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