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Flash Memory Summit 2009

Tuesday, August 11, 2009 - Friday, August 13, 2010

Connect With Micron at the Flash Memory Summit 2009

Santa Clara, California

The Flash Memory Summit is a great opportunity to connect with Micron experts and get insights into NAND Flash developments, specifications, and design considerations.

Keynote Presentation


The Many Flavors of NAND...and More to Come, Brian Shirley – Vice President of Memory
Thursday, August 13 11:00 a.m. to 11:30 a.m.

Brian Shirley – VP of Memory It’s no accident that there are as many flavors of NAND as there are usage scenarios for employing a non-volatile memory solution. Each application seeks significantly different performance parameters and feature-sets and should be designed using the right NAND to achieve optimum performance. Mr. Shirley will present on the many flavors of NAND, and the challenges of aligning the right technology with the right application. In his keynote he will also address the challenges and opportunities still to come in NAND from shrinking process technology to growing bits per cell. One thing is for certain, NAND flash innovation and opportunities continue to thrive.

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Micron Presentations


Improving Power Budgeting Estimates in NAND Applications, Michael Abraham, Applications Engineering Manager
Tuesday, August 11 8:30 a.m. to 11:20 a.m. Forum F1A
Current NAND Flash ICC specifications do not give an accurate representation of active system power. This presentation shows a better approach to measuring ICC that provides better predictability in the system of how much current devices will draw. This methodology is particularly useful for battery powered applications like mobile phones, MP3 players, and GPS units as well as large-scale NAND solutions like SSDs.

Accommodating Solid State Storage in Your Favorite OS, Justin Sykes, SSD Marketing Director
Tuesday, August 11 8:30 a.m. to 11:20 a.m. Forum F1B
This tutorial will take a detailed look at how the current operating systems present data to storage devices and how this impacts the way a NAND flash based SSD must manage the data internally. Many aspects of the way the operating system interacts with the storage device leave room for optimization when using an SSD. This secession will discuss methods of efficiently using the trim command, SSD defragmentation, optimizing sector size, and tagging of hot data. For each of these topics we will discuss how the SSD performance or endurance would be improved.

3BPC and 4BPC NAND Flash Power Requirements, Terry Grunzke, Sr. Applications Engineer
Wednesday, August 12 8:30 a.m. to 9:45 a.m. Session 101
3 BPC and 4BPC NAND FLASH can provide a lower cost solution for applications vs. SLC and MLC solutions. One of the perceived tradeoffs for the cost savings is increased power consumption. Does increased power consumption really exist and if it does what is the magnitude of increase in comparison to SLC and MLC solutions as well as HDDs? This presentation discusses power consumption topics with using 3BPC and 4BPC NAND Flash.

ONFI Update: Tastes Great, Less Filling, Jim Cooke, Sr. Marketing Manager - NAND Flash
Wednesday, August 12 8:30 a.m. to 10:50 a.m. Tutorial T1A
This session will provide an update on the Open NAND Flash Interface (ONFi) and specifically the enhancements to the new 2.1 specification, including:
  • Interface speed increased to 200MB/s
  • Low power enhancements
  • Enhanced ECC usage
  • Performance and Functionality enhancements

NAND Flash Architecture and Specification Trends, Michael Abraham, Applications Engineering Manager
Wednesday, August 12 3:15 p.m. to 5:30 p.m. Tutorial T2A
As NAND Flash continues to shrink, page sizes, block sizes, and ECC requirements are increasing while data retention, endurance, and performance are decreasing. These changes impact systems including random write performance and more. Learn how to prepare for these changes and counteract some of them through improved block management techniques and system design. This presentation also discusses some of the tradeoff myths – for example, the myth that you can directly trade ECC for endurance.

3Bit Per Cell NAND Flash, Terry Grunzke, Senior Applications Engineer
Wednesday, August 12 3:15 p.m. to 5:30 p.m. Tutorial T2A
3 BPC NAND FLASH can provide a lower cost solution for applications vs. SLC and MLC solutions, but there are tradeoffs for the cost savings. The tradeoffs include possible reduced performance, lower endurance along with reliability concerns and increased ECC requirements. This presentation discusses applications and system requirements for 3BPC NAND FLASH use.

NAND Flash Considerations for Consumer Applications, Carla Lay, Applications Engineer
Thursday, August 13 2:00 p.m. to 3:00 p.m. Session 204 -Consumer Applications II
The requirements for NAND Flash in consumer devices are highly dependent on application use conditions including typical file sizes, frequency of file updates, total and available device capacity, and required life. This presentation will discuss the resulting NAND Flash requirements, such as NAND endurance, data retention, and ECC requirements, in relation to various end-system usage scenarios.