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HMC Arrives Just in Time to Be Your New Standard for Memory Performance: Part 2

Tom Kinsley   |   November 14, 2013   |   All Products

In my last post, I touched on some obstacles of traditional memory for system designers and hinted at the reasons why so many companies have selected Hybrid Memory Cube (HMC) as their new standard for memory performance. Here, let’s start to break down some of the key features—including abstracted memory,  unique interface, and superior performance—that make HMC such a breakthrough solution.

Abstracted Memory Management and Communication

The standard DDR4 data sheet exceeds 200 pages with complex timing and signaling variations defined for multiple speed grades. On the other hand, the HMC data sheet has no memory timing requirements; no RAS, CAS, WE, and CS signals; no refresh requirements; no tFAW, tRP, tWR, and tRC restrictions; and no slew rate adjustments for voltage or bus loading variations. HMC is agnostic to memory; it can support any memory type without changes to the protocol. The standardized communication protocol defined by the Hybrid Memory Cube Consortium (HMCC) supports multiple READ, WRITE, and ATOMIC commands within a reliable packet with a header and tail that provide data routing between the host and all cubes within the channel. The protocol is simple and adaptive to future HMC devices.

High-level HMC block diagram

Simple and Scalable Interface

Traditional memory channels have wide interfaces that run multiple devices in lockstep, are extremely sensitive to signal loading, and require coordinated accesses to prevent bus contention. HMC uses high-speed serial/deserializer (SERDES) channels to interface to the outside world. These channels run directly between devices and can operate independently of each other, yet can talk to any memory location within the cube. Each HMC lane runs at 10 Gb/s, 12.5 Gb/s, or 15 Gb/s with multiple channel configurations to support almost any bandwidth requirement up to 160 GB/s per cube. Not only does the cube provide bandwidth scalability, it also supports cube-to-cube chaining to increase memory density without increasing the pin count of the host.

Superior and Sustainable Performance

Before HMC, it was impossible to sustain 160 GB/s (that’s 1.28Tb!) of memory bandwidth—all day long. It took the efforts of many accomplished engineers, working for several years, to resolve the well-documented “memory wall” problem with HMC. The HMC stack consists of four or eight memory layers and one logic layer. The memory is based on our high-volume process node but designed just for HMC. Each memory layer has millions of memory cells in defined groups (vaults) with complex support logic (vault controller) that controls all aspects of the memory cells and provides an interface to the internal crossbar switch. The logic die is manufactured at a world-class logic foundry so we can maximize the density of the memory layers and take advantage of the predictability of the logic process to ensure robust vault controllers. HMC has 16 vaults that operate independently of each other and are designed to sustain 10 GB/s (80 Gb/s) of true memory bandwidth from each vault. The logic layer also supports the external interfaces, cross-bar switch, memory schedulers, built-in self-test (BIST), sideband channels, and numerous reliability, availability, and serviceability (RAS) features.

There’s more! Keep an eye out for my next post where I’ll discuss these additional HMC features:

  • Uncomplicated board layout and dense package
  • Exceptional RAS features
  • Low total cost of ownership (TCO)
  • Stable technology and long-term support

If you have any questions or thoughts about today’s post, please leave a comment below.

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